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openhwgroup / cv32e40s

4 stage, in-order, secure RISC-V core based on the CV32E40P
https://docs.openhwgroup.org/projects/cv32e40s-user-manual/en/latest/
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Merge from cv32e40x #521

Closed silabs-oysteink closed 10 months ago

silabs-oysteink commented 10 months ago

Includes fix for mret + mcause.minhv and the needed CSR updates for that scenario.

SEC clean when mcause.minhv is assumed to be zero.