Bug while compiling CV32E40S model with core-v-verif

[pcotret]

Bug Title

Bug while compiling CV32E40S model with core-v-verif. See issue https://github.com/openhwgroup/core-v-verif/issues/2362

Component

Indicate the component in which you found a problem (and we will add the appropriate label):

Component:RTL: For issues in the RTL (e.g. for files in the rtl directory)

Steps to Reproduce

git clone https://github.com/openhwgroup/core-v-verif
cd core-v-verif/cv32e40s/sim/core 
export CV_CORE=cv32e40s 
export CV_SW_PREFIX=riscv32-unknown-elf-
export CV_SW_TOOLCHAIN=/opt/corev-openhw 
export PATH=/opt/corev-openhw/bin:$PATH
make

Generates this error:

%Error: /home/pascal/core-v-verif/core-v-cores/cv32e40s/rtl/cv32e40s_register_file_wrapper.sv:85:35: syntax error, unexpected ')', expecting "'{"
   85 |     assign rdata_o[i] = (rf_data_t)'(rf_rdata[i][REGFILE_DATA_WIDTH-1:0]);
      |                                   ^
%Error: Exiting due to 1 error(s)

Other information

Verilator 5.006 installed. Debian 12.

[pcotret]

https://github.com/openhwgroup/cv32e40s/commit/a122caee8108c0c54057477fe6f91864acae5861

This bug has been fixed here. I assume the issue is more on the core-v-verif side which clones a too old cv32e40s core :cry:

Issue closed.