search

openhwgroup / cv32e41p

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
https://docs.openhwgroup.org/projects/cv32e41p-user-manual/
Other
26 stars 11 forks source link

40P conditional compilation flags in the 41P #10

Closed pcotret closed 2 years ago

pcotret commented 2 years ago

Just saw that there are 40P-related compilation flags in the 41P code. Example: https://github.com/openhwgroup/cv32e41p/blob/master/bhv/cv32e41p_wrapper.sv#L14

Is there a specific reason for that?

abukharmeh commented 2 years ago

Yes, the source for 41p in this repo is just the source of 40p. In my local copy, these are gone, I would expect them to be fixed here shortly, when we start pushing source code back.