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openhwgroup / cv32e41p

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
https://docs.openhwgroup.org/projects/cv32e41p-user-manual/
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1) Update the assertions and tracer ifdefs #15

Closed abukharmeh closed 2 years ago

abukharmeh commented 2 years ago

Closes #10