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openhwgroup / cv32e41p

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
https://docs.openhwgroup.org/projects/cv32e41p-user-manual/
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5) Change PULP_ZFINX to ZFINX #21

Closed abukharmeh closed 2 years ago

abukharmeh commented 2 years ago

Following is a list of things changed in this PR:

  1. Change PULP_ZFINX parameter to ZFINX
  2. Disables F bit in MISA when ZFINX is enabled
  3. Disable floating point moves, stores and loads when ZFINX is enabled
davideschiavone commented 2 years ago

LGTM

@pascalgouedo - I suggest to cherrypick this commit for cv32e40p too