openhwgroup / cv32e41p

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
https://docs.openhwgroup.org/projects/cv32e41p-user-manual/
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7) Seq instructions #24

Open abukharmeh opened 2 years ago

abukharmeh commented 2 years ago

Adds initial implementation of the sequencer and sequenced instructions (tbljal, pushpop and double move) Adds BEQI and BNEI Fix assertions for Zext/ Sext Fix March ID

@davideschiavone Can you have a look at this one please, thank you !

NOTE: This PR finishes implementing the features of Zce v0.5 https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.50.1-TOOLCHAIN-DEV , in next sets of PRs, will tune the design and move to v0.7