check verible ci - Githubissues

openhwgroup / cv32e41p

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

https://docs.openhwgroup.org/projects/cv32e41p-user-manual/

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check verible ci #26

Open davideschiavone opened 2 years ago

davideschiavone commented 2 years ago

Adding a CI that checks the format of SystemVerilog files

abukharmeh commented 2 years ago

Hi Davide, this looks good to me, it would be nice to output the line number as well as that could make it easier to tell what is happening, but its not really important !