Implement the Zce ISA extension

openhwgroup / cv32e41p

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

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Open davideschiavone opened 3 years ago

davideschiavone commented 3 years ago

we should implement the RISC-V Zce ISA extension

This implies:

[ ] to update the documentation
[ ] to add the Parameter name
[ ] to change the RTL - the RTL must be logically equivalent to the core when the Zce parameter is set to 0

Task assigned to @tariqkurd-repo