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openhwgroup / cva5

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
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Cache architecture of the previous version (Taiga) #11

Open demyana123 opened 1 year ago

demyana123 commented 1 year ago

Hello,

In your old version of Taiga, you didn't mention at your paper of Taiga configuration ........ a specific type of your cache architecture. I have found that it is write through but now in your updated version you say that it is write back at a new paper for cva5.

could you show it to me if you have changed the architecture as firstly I worked on the old version?

e-matthews commented 1 year ago

The data-cache write policy for CVA5 is unchanged and is still write-through. The only recent changes to the data cache have been latency related (a one cycle reduction in load latency) and are currently on the accelerators-2023 branch.

demyana123 commented 1 year ago

Have you implemented the write through method with a look aside buffer to store Updated data for a while and send them to the memory or directly is sent to the main memory in each writing operation?

e-matthews commented 1 year ago

No, there is no additional buffering or coalescing of writes. Each write is sent to directly to memory when it reaches the data cache.