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openhwgroup / cva5

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
Apache License 2.0
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cva5 simulation using questasim #14

Open AhmedMostafa98 opened 1 year ago

AhmedMostafa98 commented 1 year ago

Hi, Thanks for your efforts.

I tried to run through the following path test_benchs/cva5_tb.sv, after creating a questasim makefile. But, I found out a lot of x propagations that failed the simulation. i tried to add a reset condition for all always_ff blocks in the code but still have x propagations.

e-matthews commented 1 year ago

This is most likely due to how config options are handled in CVA5. Most signals are not assigned if unused, so you will need to look for a config option for your simulator to initialize unassigned values to zero (matching the hardware behaviour). If that doesn't work, please let me know.

AhmedMostafa98 commented 1 year ago

i solved all the issues with XPROP, but the uart.log is empty after running the whole test. i don't know what is the issue exactly.

AhmedMostafa98 commented 1 year ago

could you please provide me with an example of running the design and the output ?

AhmedMostafa98 commented 1 year ago

Kindly reminder

e-matthews commented 1 year ago

The best starting place for an example would be the CVA5-accelerators repo https://github.com/openhwgroup/cva5-accelerators

It includes pre-built embench binaries and a setup for running embench benchmarks using Verilator and on an FPGA board (Nexys A7).

Another option is: https://gitlab.com/sfu-rcl/taiga-project Which provides setup for GCC, picolibc (as the C library) verilator as well as some benchmarks.

The software support in both repos assumes that there is a Xilinx UART as part of the system, with all printfs being outputting to the UART. The cva5-accelerators repo contains an example output for the UART as well.

AhmedMostafa98 commented 1 year ago

so, if i don't have UART system integrated with your implementation, the output won't appear ?