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openhwgroup / cva5

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
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AXI DDR #15

Closed maheshejs closed 1 year ago

maheshejs commented 1 year ago

Hi!

I'm wondering if the AXI DDR simulation supports write and read bursts.

Thanks.

CKeilbar commented 1 year ago

Yes, the AXI DDR simulation supports both write and read bursts by using the number_of_bursts_left variable.