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openhwgroup / cva5

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
Apache License 2.0
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Clarification Regarding Simulation of CVA-5 Processor #24

Open Tanishqgithub opened 8 months ago

Tanishqgithub commented 8 months ago

Respected sir Subject: Request for Assistance - CVA-5 Processor Simulation

I trust this email finds you well. My name is Tanishq.S, and I am a student from PES University, India. I am reaching out along with my team as we are currently engaged in a Capstone project focusing on the analysis of the CVA-5 Processor Performance . To apply our Concepts we have to analyze all the internal signals of the processor so we choose simulating in Xilinx Vivado and we could not simulate successfully .

I have a few specific queries that I believe your expertise could help address:

  1. Design File (cva5.sv):

    • Could you please provide clarity on the necessary files in the GitHub repository required for the design file (cva5.sv) {Top Module}? We are particularly interested in identifying the key dependencies and components essential for the successful execution of the top module.

  2. TestBench File (cva5_tb.sv):

    • Similarly, we would appreciate guidance on the required files in the GitHub repository for the testbench file (cva5_tb.sv){Top Module}. Understanding the dependencies and necessary components for the top module in the testbench would greatly assist us in overcoming our current simulation challenges.

  3. Providing Our Own C File:

    • Our intention is to incorporate our own C file into the simulation for a more targeted analysis of the processor's performance. Could you please guide us on the process of providing our C file to the processor for analysis of the output obtained through the simulation window?

Regarding the testbench file, we observed that a default memory file path was used: "/home/ematthew/Research/RISCV/software/riscv-tools/riscv-tests/benchmarks/dhrystone.riscv.hw_init." Is this where we should specify the path to our own C file for analysis, or is there a different procedure we should follow?

  1. And along with the above Guidance Please also give assistance in concept of use of "parameter cpu_config_t CONFIG = EXAMPLE_CONFIG" in some files present in the Github Repository

Your assistance in these matters would be invaluable to our project, and we are eager to learn from your expertise. We are grateful for any guidance you can provide and assure you that your support will not be forgotten.

Thank you for considering our request. We look forward to your response.

Best regards,

Tanishq.S PES UNIVERSITY , INDIA

CKeilbar commented 7 months ago

Hello, I am sorry for the delayed response. I suggest you use the accelerators-2023 branch for your work, it is the most recent version and has several useful changes.

  1. The primary dependencies are everything in the core, l2_arbiter, and local_memory directories.
  2. I don't think the testbench is up to date and it might not work. You shouldn't need to use it.
  3. Your best method to run a C program is through these repositories: https://gitlab.com/sfu-rcl/taiga-project https://gitlab.com/sfu-rcl/taiga-example-c-project. It provides the build environment and an example C program that you can run. The process to run a simulation requires building the processor executable using verilator and providing the compiled code (specified in hex format as a .hw_init file) as an argument to the simulator at runtime. You can enable tracing in your simulator and can view the generated .vcd file in a waveform viewer.
  4. The cpu_config_t struct is used to configure the processor and the components are largely self-explanatory. In the simulation, the top-level component is the nexys_sim.sv file which uses nexys_config.sv