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openhwgroup / cva5

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
Apache License 2.0
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Regarding Simulation of 'make run-example-c-project-verilator' in GitLab for CVA-5 #25

Open Tanishqgithub opened 5 months ago

Tanishqgithub commented 5 months ago

Respected sir I trust this email finds you well. My name is Tanishq.S, and I am a student from PES University, India. I am reaching out along with my team as we are currently engaged in a Capstone project focusing on the analysis of the CVA-5 Processor Performance . After installing the toolchain and running the make file "make run-example-c-project-verilator" i got this 9errors and 5 warnings :

{Please see the Error obtained in the Screenshots attached to this ISSUE}

ERROR_3rd_Screenshot

Y

ERROR_2nd_Screenshot ERROR_1st_Screenshot

our assistance in these matters would be invaluable to our project, and we are eager to learn from your expertise. We are grateful for any guidance you can provide and assure you that your support will not be forgotten.

Thank you for considering our request. We look forward to your response.

Best regards,

Tanishq.S PES UNIVERSITY , INDIA +91 8050375861

ERROR OBTAINED : tanishq@Tanishq:~/Documents/CVA-5/taiga-project$ make run-example-c-project-verilator

mkdir -p /home/tanishq/Documents/CVA-5/taiga-project/cva5/test_benches/verilator/build

verilator --cc --exe --Mdir /home/tanishq/Documents/CVA-5/taiga-project/cva5/test_benches/verilator/build -DENABLE_SIMULATION_ASSERTIONS --assert \

-o cva5-sim \

-Wno-LITENDIAN -Wno-SYMRSVDWORD --CFLAGS "-g0 -O3 -std=c++14 -march=native -DDDR_SIZE=(long)4(long)1073741824 -DPAGE_SIZE=(21024) -DMAX_INFLIGHT_RD_REQ=8 -DMAX_INFLIGHT_WR_REQ=8 -DMIN_DELAY_RD=1 -DMAX_DELAY_RD=1 -DMIN_DELAY_WR=1 -DMAX_DELAY_WR=1 -DDELAY_SEED=867583" \

/home/tanishq/Documents/CVA-5/taiga-project/cva5/test_benches/verilator/CVA5Tracer.cc /home/tanishq/Documents/CVA-5/taiga-project/cva5/test_benches/verilator/SimMem.cc /home/tanishq/Documents/CVA-5/taiga-project/cva5/test_benches/verilator/cva5_sim.cc /home/tanishq/Documents/CVA-5/taiga-project/cva5/test_benches/verilator/AXI_DDR_simulation/axi_ddr_sim.cc /home/tanishq/Documents/CVA-5/taiga-project/cva5/test_benches/verilator/AXI_DDR_simulation/ddr_page.cc \

/home/tanishq/Documents/CVA-5/taiga-project/cva5/core/cva5_config.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/riscv_types.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/csr_types.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/cva5_types.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/l2_arbiter/l2_config_and_types.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/l2_arbiter/l2_interfaces.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/l2_arbiter/l2_external_interfaces.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/local_memory/local_memory_interface.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/local_memory/local_mem.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/interfaces.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/external_interfaces.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/lutrams/lutram_1w_1r.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/lutrams/lutram_1w_mr.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/lfsr.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/csr_unit.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/gc_unit.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/branch_comparator.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/branch_unit.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/barrel_shifter.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/alu_unit.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/axi_master.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/avalon_master.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/wishbone_master.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/axi_to_arb.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/one_hot_occupancy.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/binary_occupancy.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/cva5_fifo.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/shift_counter.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/priority_encoder.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/set_clr_reg_with_rst.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/intel/intel_byte_enable_ram.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/xilinx/xilinx_byte_enable_ram.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/byte_en_BRAM.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/one_hot_to_integer.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/cycler.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/tag_bank.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/dbram.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/ddata_bank.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/dtag_banks.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/amo_alu.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/dcache.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/addr_hash.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/load_queue.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/store_queue.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/load_store_queue.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/load_store_unit.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/ibram.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/itag_banks.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/icache.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/clz.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/div_core.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/div_unit.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/tlb_lut_ram.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/mmu.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/mul_unit.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/l1_arbiter.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/ras.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/branch_predictor_ram.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/branch_predictor.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/fetch.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/illegal_instruction_checker.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/decode_and_issue.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/register_free_list.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/renamer.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/register_bank.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/register_file.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/writeback.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/placer_randomizer.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/l2_arbiter/l2_fifo.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/l2_arbiter/l2_reservation_logic.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/l2_arbiter/l2_round_robin.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/l2_arbiter/l2_arbiter.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/toggle_memory.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/toggle_memory_set.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/instruction_metadata_and_id_management.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/cva5.sv /home/tanishq/Documents/CVA-5/taiga-project/cva5/test_benches/verilator/cva5_sim.sv --top-module cva5_sim

%Error: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/writeback.sv:78:89: Member selection of non-struct/union object 'ARRAYSEL' which is a 'IFACEREFDTYPE'

                                                                            : ... In instance cva5_sim.cpu.writeback_block

78 | assign unit_instruction_id[i][j] = unit_wb[CUMULATIVE_NUM_UNITS[i] + j].id;

  |                                                                                         ^~

%Warning-WIDTH: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/writeback.sv:78:50: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '1'h0' generates 1 bits.

                                                                                    : ... In instance cva5_sim.cpu.writeback_block

78 | assign unit_instruction_id[i][j] = unit_wb[CUMULATIVE_NUM_UNITS[i] + j].id;

  |                                                  ^

            ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.

%Error: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/writeback.sv:79:79: Member selection of non-struct/union object 'ARRAYSEL' which is a 'IFACEREFDTYPE'

                                                                            : ... In instance cva5_sim.cpu.writeback_block

79 | assign unit_done[i][j] = unit_wb[CUMULATIVE_NUM_UNITS[i] + j].done;

  |                                                                               ^~~~

%Error: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/writeback.sv:80:61: Member selection of non-struct/union object 'ARRAYSEL' which is a 'IFACEREFDTYPE'

                                                                            : ... In instance cva5_sim.cpu.writeback_block

80 | assign unit_wb[CUMULATIVE_NUM_UNITS[i] + j].ack = unit_ack[i][j];

  |                                                             ^~~

%Error: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/writeback.sv:90:77: Member selection of non-struct/union object 'ARRAYSEL' which is a 'IFACEREFDTYPE'

                                                                            : ... In instance cva5_sim.cpu.writeback_block

90 | assign unit_rd[i][j] = unit_wb[CUMULATIVE_NUM_UNITS[i] + j].rd;

  |                                                                             ^~

%Warning-WIDTH: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/writeback.sv:90:38: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS's CONST '1'h0' generates 1 bits.

                                                                                    : ... In instance cva5_sim.cpu.writeback_block

90 | assign unit_rd[i][j] = unit_wb[CUMULATIVE_NUM_UNITS[i] + j].rd;

  |                                      ^

%Error: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/gc_unit.sv:238:52: Member selection of non-struct/union object 'ARRAYSEL' which is a 'IFACEREFDTYPE'

                                                                           : ... In instance cva5_sim.cpu.gc_unit_block

238 | assign exception_pending[i] = exception[i].valid;

  |                                                    ^~~~~

%Error: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/gc_unit.sv:239:49: Member selection of non-struct/union object 'ARRAYSEL' which is a 'IFACEREFDTYPE'

                                                                           : ... In instance cva5_sim.cpu.gc_unit_block

239 | assign exception_code[i] = exception[i].code;

  |                                                 ^~~~

%Warning-WIDTH: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/gc_unit.sv:239:34: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's CONST '1'h0' generates 1 bits.

                                                                                   : ... In instance cva5_sim.cpu.gc_unit_block

239 | assign exception_code[i] = exception[i].code;

  |                                  ^

%Error: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/gc_unit.sv:240:47: Member selection of non-struct/union object 'ARRAYSEL' which is a 'IFACEREFDTYPE'

                                                                           : ... In instance cva5_sim.cpu.gc_unit_block

240 | assign exception_id[i] = exception[i].id;

  |                                               ^~

%Warning-WIDTH: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/gc_unit.sv:240:32: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '1'h0' generates 1 bits.

                                                                                   : ... In instance cva5_sim.cpu.gc_unit_block

240 | assign exception_id[i] = exception[i].id;

  |                                ^

%Error: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/gc_unit.sv:241:49: Member selection of non-struct/union object 'ARRAYSEL' which is a 'IFACEREFDTYPE'

                                                                           : ... In instance cva5_sim.cpu.gc_unit_block

241 | assign exception_tval[i] = exception[i].tval;

  |                                                 ^~~~

%Warning-WIDTH: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/gc_unit.sv:241:34: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS's CONST '1'h0' generates 1 bits.

                                                                                   : ... In instance cva5_sim.cpu.gc_unit_block

241 | assign exception_tval[i] = exception[i].tval;

  |                                  ^

%Error: /home/tanishq/Documents/CVA-5/taiga-project/cva5/core/gc_unit.sv:242:29: Member selection of non-struct/union object 'ARRAYSEL' which is a 'IFACEREFDTYPE'

                                                                           : ... In instance cva5_sim.cpu.gc_unit_block

242 | assign exception[i].ack = exception_ack;

  |                             ^~~

%Error: Exiting due to 9 error(s), 5 warning(s)

make: *** [/home/tanishq/Documents/CVA-5/taiga-project/cva5/tools/cva5.mak:90: /home/tanishq/Documents/CVA-5/taiga-project/cva5/test_benches/verilator/build/cva5-sim] Error 1

tanishq@Tanishq:~/Documents/CVA-5/taiga-project$

CKeilbar commented 4 months ago

Interesting; I have never seen those errors. Which version of Verilator are you using? If it is an older one, you can try compiling a newer version of Verilator from source. I can confirm that Verilator 5.018 works.