openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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Questasim uvm_dpi.so #10

Closed lfernand4 closed 6 years ago

lfernand4 commented 6 years ago

HI,

I have build the TB and module with questasim 10.6c_3. I start the simulation : make simc (without GUI) image

I have the following warning : image

Now I run (run -a) : image

How can I solve this error ? where does it come from ? I have only add -64 in the scipt.

Thanks in advance.

raulbehl commented 6 years ago

Even I am seeing the same issue. I do see in the Makefile that the C-code is compiled using the vlog command only:

# build TBs
$(library)/.build-tb: $(dpi) $(tbs)
    # Compile top level with DPI headers
    vlog$(questa_version) -sv $(tbs) -work $(library) $(filter %.c %.cc, $(dpi)) -ccflags "-g -std=c++11 " -dpiheader tb/dpi/elfdpi.h
    touch $(library)/.build-tb

Questasim should have been able to load the compiled .so files automatically but for some reason it is not doing that. As a work around to get things working, I did the following:

lfernand4 commented 6 years ago

Thanks for explanations. Now I want to run dhrystone, do you know how to do it ? I have compiled in .elf (.riscv). I feel I need a .hex. It is correct ?

zarubaf commented 6 years ago

Yes, I've added some documentation on that in the README.md. elf2hex 8 2097152 elf_file.riscv 2147483648 > elf_file.riscv.hex`

zarubaf commented 6 years ago

@raulbehl Thanks for clarifying the issue with DPI. I think I will investigate a better approach to that, considering something like you did (not using Questa for it).

raulbehl commented 6 years ago

@zarubaf thank you for the comment. Along with the DPI change, the vsim command in the Makefile also needs the "-64" option passed to it. Otherwise questa complains that the code was compiled with 64-bit support but is not simulated with it.

Also, would it be okay if I add the above mentioned changes to handle DPI calls in the Makefile and open a pull request for the same? You could then add your fixes on top of it assuming those are on the similar lines.

lfernand4 commented 6 years ago

I have generate Dhrystone.riscv.elf and Dhrystone.riscv.hex.

command :

vsim -lib work core_tb_optimized "+UVM_TESTNAME=core_test" "+BASEDIR=/prj/xpuips/riscv/riscv-tools/riscv-tests/benchmarks" "+ASMTEST=dhrystone.riscv" "+UVM_NO_RELNOTES" "+UVM_VERBOSITY=HIGH" -coverage -classdebug -sv_lib tb/dpi/elf_dpi -do "do tb/wave/wave_core.do"  

I have this error in questasim :

capture

How can I solve this error ? where does it come from ?

Thanks in advance.

zarubaf commented 6 years ago

@lfernand4 See issue #7 @raulbehl I would be more than happy to accept such a PR. Thanks!