openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
Other
2.21k stars 673 forks source link

[TASK] ISA DV plan for embedded config ISA #1397

Open JeanRochCoulon opened 1 year ago

JeanRochCoulon commented 1 year ago

What (objective description) ? Create ISA DV plan for embedded config ISA.

How to ? Use the ISA DV plan of the Step1 configuration , and add to it the new instructions.

Current Status ? None.

Risks ? None

Prerequisites ? Zicond, Zce, Zb spec

KPI ? None

Description of done? DV plan for embedded config ISA approuved by Jean-Roch.

JeanRochCoulon commented 11 months ago

@AyoubJalali Is this task started ? Change the status if it is the case. If you need prerequisites (Zicond, Zce, Zb specs), do not hesitate to ask for during the CVA6 (Tomorrow) meeting.

AyoubJalali commented 11 months ago

@AyoubJalali Is this task started ? Change the status if it is the case. If you need prerequisites (Zicond, Zce, Zb specs), do not hesitate to ask for during the CVA6 (Tomorrow) meeting.

of course

AyoubJalali commented 11 months ago

Ready to be approved

AyoubJalali commented 10 months ago

the zicond & zcb extension are add it to the ISA dvplan by PR #1618