Closed zchamski closed 1 week ago
A working version of the Tandem has been pushed to my repo that implements the following:
Tandem rebased to last cva6/master commit. It is working on Centos 7 and Debian 10.
Some discussion needed regarding integration corev_apu/tb/common/Sim*.cc
into riscv-isa-sim
Fixing Github CI in order to merge. Also fixing the issues commented in both PRs.
CI has been fixed and it shows green on Thales CI and on Github
PR has been merged already
On going efforts to make the tandem available on verilator
I am working on make verilator work on 64bits but it has issues in the DPI interface
This task is mostly finished, CSRs need to be integrated too.
Needs to be discussed correctly if we want to compare all the csrs or just the modified ones.
Task completed for CV32A65X. Adding other configurations is a matter of providing the necessary configuration files for Spike, and possibly, of adding futher configurability if needed.
Background
Lockstep ("tandem") co-simulation allows early detection of divergences between behaviors of different simulation models on the same test case. Typically, an Instruction Set Simulator (ISS) and an RTL simulator are fed with the same binary program. The simulation can be stopped as soon as a divergence is detected, or can be pursued for a controlled amount of steps (instruction commits + exceptions) to observe the consequences of the divergence.
For CVA6, the current ISS simulator is Spike and the primary RTL simulator is VCS, set up in either "test harness" or full UVM mode.
What (objective description)
Build a software system in which Spike and VCS simulations are executed concurrently and the observable state of both models is compared at every instruction commit and at every exception triggered.
How To
Current Status
In progress. Working prototype available for
vcs-testharness
andvcs-uvm
, but it only compares PC values, instruction content, and GPR and memory writes.Risks
TBD
Prerequisites
Dependency on completion of #1402 and #1384. For the Embedded configuration additional dependency on #1403.
KPI
TBD
Description of DONE
Identical set of PASS and FAIL results on CI tests between full trace comparison and lockstep simulation.