[BUG] UVM failed on questa Sim

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

https://docs.openhwgroup.org/projects/cva6-user-manual/

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[BUG] UVM failed on questa Sim #1533

Closed AnikBalo closed 11 months ago

AnikBalo commented 1 year ago

Is there an existing CVA6 bug for this?

[X] I have searched the existing bug issues

Bug Description

Hi, I was trying to simulate CVA6 in questaSim. While running the command: "make sim elf-bin=" I am not getting any error but UVM FAILED. Actually, I want to generate the activity file from the simulation. Any idea if this is okay or how to debug this issue? Thanks!

The output: uvm_error

JeanRochCoulon commented 1 year ago

Hello As you can read in README.md, make sim is not the right way to simulate the CVA6. You should use cva6.py command. But on my side, I use only VCS and verilator, I cannot confirm the Questasim is fully functional, but I wold be pleased to get your feedback.

AnikBalo commented 1 year ago

@JeanRochCoulon I thnik CVA6 section has been removed from core-v-verif repository.

JeanRochCoulon commented 1 year ago

The README.md with the commands to be executed is in cva6 repo (and not core-v-verif)

github-actions[bot] commented 11 months ago

👋 Hi there!

This issue seems inactive. Need more help? Feel free to update us. If there are no updates within the next few days, we'll go ahead and close this issue. 😊

valentinThomazic commented 11 months ago

Hi, did you manage to solve your issue ?

JeanRochCoulon commented 11 months ago

Hello @AnikBalo Today Questa is not supported by CVA6 repository. If you are ready to contribute the target questa-testharness can be updated to work. I propose to close this issue becasue it is not supported.