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openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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Getting assertion error during simulation of cva6 using Questasim #1619

Closed UsamaEmam closed 10 months ago

UsamaEmam commented 10 months ago

Getting assertion error during simulation of the latest version of cva6 on the master using Questasim The failing assertion in core/pmp/src/pmp.sv : image

The assertion fails only once during simulation but the test finishes and triggered the following UVM INFO in corev_apu/tb/ariane_tb.sv: image

Is this assertion accepted? or how to avoid such scenario?

MikeOpenHWGroup commented 10 months ago

Hi @UsamaEmam, thanks for your issue. Can you update this issue with the exact command-lines you used starting with git clone....? This will be a big help to debug the issue. Also, please let us know the version of Questasim.

Hi @Moschn, you are the original author of this assertion, can you comment on its purpose? Should the testcase fail if the assertion fires?

zarubaf commented 10 months ago

Yeah, this is an intermittent assertions that fires before reset, so can be ignored. But should be fixed for a cleaner flow.