Guidance to simulate CVA6

I would like to simulate CVA6 with Verilator and I am in need of some guidance as I have little to no experience on these matters. First, Is this is the place to ask such questions or I should look elsewhere?

I am working under Ubuntu 22.04.2. This is what I’ve done so far:

I installed the RISCV toolchain from here: https://github.com/riscv-collab/riscv-gnu-toolchain/releases, specifically: riscv64-elf-ubuntu-22.04-gcc-nightly-2023.11.08. I followed this instructions: https://github.com/stnolting/riscv-gcc-prebuilt
Then I set $RISCV to /opt/riscv and added /opt/riscv/bin to path.
I installed Spike and Riscv-PK and compiled and simulated a hello world following this video: https://www.youtube.com/watch?v=zZUtTplVHwE&ab_channel=DerryPratama These are the gcc and toolchain versions: $ gcc --version gcc (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0 Copyright (C) 2021 Free Software Foundation, Inc. $ riscv64-unknown-elf-gcc --version riscv64-unknown-elf-gcc () 13.2.0 Copyright (C) 2023 Free Software Foundation, Inc. I tried to follow the “Getting Started” instructions:
I cloned the CVA6 repository
I ran the following: $export DV_SIMULATORS=veri-testharness,spike $bash verif/regress/smoke-tests.sh But it did not find verilator, so I added it to path by running: $export PATH=$PATH:/home/username/Documents/cva6Repo/tools/verilator-v5.008/verilator/bin

Then I executed: $bash verif/regress/smoke-tests.sh and I don’t know how to interpret the output. I see some lines mentioning errors, such as: ERROR ERROR return code: True/2, cmd:make veri-testharness target=cv32a60x

The output is at the end of this message, I had to take a section out because it would not fit in a single message.

Any help would be greatly appreciated.

Output:

``` Building Verilator in /home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator... Verilator will be installed in /home/username/Documentos/cva6Repo/tools/verilator-v5.008 VERILATOR_REPO=https://github.com/verilator/verilator.git VERILATOR_BRANCH=master VERILATOR_HASH=v5.008 VERILATOR_PATCH=/home/username/Documentos/cva6Repo/tools/../verif/regress/verilator-v5.patch NUM_JOBS=4 M docs/CONTRIBUTORS M include/verilated_types.h HEAD está ahora en 21093fd1b Version bump error: patch failed: docs/CONTRIBUTORS:154 error: docs/CONTRIBUTORS: patch does not apply error: patch failed: include/verilated_types.h:1012 error: include/verilated_types.h: patch does not apply configuring for Verilator 5.008 2023-03-04 checking whether to perform partial static linking of Verilator binary... yes checking whether to use tcmalloc... check checking whether to use -m32... no checking whether to build for coverage collection... no checking whether to use hardcoded paths... yes checking whether to show and stop on compilation warnings... no checking whether to run long tests... no checking for gcc... gcc checking whether the C compiler works... yes checking for C compiler default output file name... a.out checking for suffix of executables... checking whether we are cross compiling... no checking for suffix of object files... o checking whether the compiler supports GNU C... yes checking whether gcc accepts -g... yes checking for gcc option to enable C11 features... none needed checking for g++... g++ checking whether the compiler supports GNU C++... yes checking whether g++ accepts -g... yes checking for g++ option to enable C++11 features... none needed checking for a BSD-compatible install... /usr/bin/install -c compiler is g++ --version = g++ (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0 checking that C++ compiler can compile simple program... yes checking for ar... ar checking for perl... /usr/bin/perl checking for python3... /usr/bin/python3 checking for flex... /usr/bin/flex /usr/bin/flex --version = flex 2.6.4 checking for bison... /usr/bin/bison /usr/bin/bison --version = bison (GNU Bison) 3.8.2 checking for ccache... no checking for stdio.h... yes checking for stdlib.h... yes checking for string.h... yes checking for inttypes.h... yes checking for stdint.h... yes checking for strings.h... yes checking for sys/stat.h... yes checking for sys/types.h... yes checking for unistd.h... yes checking for size_t... yes checking for size_t... (cached) yes checking for inline... inline checking whether g++ accepts -pg... yes checking whether g++ accepts -std=gnu++17... yes checking whether g++ accepts -Wextra... yes checking whether g++ accepts -Wfloat-conversion... yes checking whether g++ accepts -Wlogical-op... yes checking whether g++ accepts -Wthread-safety... no checking whether g++ accepts -fcoroutines-ts... no checking whether coroutines are supported by g++... yes checking whether g++ accepts -Qunused-arguments... no checking whether g++ accepts -faligned-new... yes checking whether g++ accepts -Wno-unused-parameter... yes checking whether g++ accepts -Wno-shadow... yes checking whether g++ accepts -Wno-char-subscripts... yes checking whether g++ accepts -Wno-null-conversion... no checking whether g++ accepts -Wno-parentheses-equality... no checking whether g++ accepts -Wno-unused... yes checking whether g++ accepts -Og... yes checking whether g++ accepts -ggdb... yes checking whether g++ accepts -gz... yes checking whether g++ linker accepts -gz... yes checking whether g++ accepts -faligned-new... yes checking whether g++ accepts -fbracket-depth=4096... no checking whether g++ accepts -fcf-protection=none... yes checking whether g++ accepts -mno-cet... no checking whether g++ accepts -Qunused-arguments... no checking whether g++ accepts -Wno-bool-operation... yes checking whether g++ accepts -Wno-tautological-bitwise-compare... no checking whether g++ accepts -Wno-parentheses-equality... no checking whether g++ accepts -Wno-sign-compare... yes checking whether g++ accepts -Wno-uninitialized... yes checking whether g++ accepts -Wno-unused-but-set-variable... yes checking whether g++ accepts -Wno-unused-parameter... yes checking whether g++ accepts -Wno-unused-variable... yes checking whether g++ accepts -Wno-shadow... yes checking whether g++ linker accepts -mt... no checking whether g++ linker accepts -pthread... yes checking whether g++ linker accepts -lpthread... yes checking whether g++ linker accepts -latomic... yes checking whether g++ linker accepts -static-libgcc... yes checking whether g++ linker accepts -static-libstdc++... yes checking whether g++ linker accepts -Xlinker -gc-sections... yes checking whether g++ linker accepts -lpthread... yes checking whether g++ linker accepts -lbcrypt... no checking whether g++ linker accepts -lpsapi... no checking whether g++ linker accepts -l:libtcmalloc_minimal.a... no checking whether g++ supports C++11... yes checking for struct stat.st_mtim.tv_nsec... yes checking whether SystemC is found (in system path)... yes configure: creating ./config.status config.status: creating Makefile config.status: creating src/Makefile config.status: creating src/Makefile_obj config.status: creating include/verilated.mk config.status: creating include/verilated_config.h config.status: creating verilator.pc config.status: creating verilator-config.cmake config.status: creating verilator-config-version.cmake config.status: creating src/config_build.h config.status: src/config_build.h is unchanged Now type 'make' (or sometimes 'gmake') to build Verilator. help2man --no-info --no-discard-stderr --version-string=- bin/verilator_gantt -o verilator_gantt.1 make: help2man: File or directory does not exist make: *** [Makefile:191: verilator_gantt.1] Error 127 make: *** Waiting for other tasks to finish.... ------------------------------------------------------------ making verilator in src make -C src make[1]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src' make -C obj_dbg -j 1 TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj serial make -C obj_dbg TGT=../../bin/verilator_coverage_bin_dbg VL_DEBUG=1 VL_VLCOV=1 -f ../Makefile_obj serial_vlcov make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src' make[2]: attention: forcing a -j1 en el submake: se restablece el modo de servidor de tareas. make -C obj_opt -j 1 TGT=../../bin/verilator_bin -f ../Makefile_obj serial make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src' make[2]: attention: forcing a -j1 en el submake: se restablece el modo de servidor de tareas. make[2]: Nothing is done for 'serial'. make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make -C obj_dbg TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make[2]: Nothing is done for 'serial_vlcov'. make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make[2]: Nothing is done for 'serial'. make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_opt' make -C obj_dbg TGT=../../bin/verilator_coverage_bin_dbg VL_DEBUG=1 VL_VLCOV=1 -f ../Makefile_obj make -C obj_opt TGT=../../bin/verilator_bin -f ../Makefile_obj make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -DDEFENV_SYSTEMC=\"\" -DDEFENV_SYSTEMC_ARCH=\"\" -DDEFENV_SYSTEMC_INCLUDE=\"\" -DDEFENV_SYSTEMC_LIBDIR=\"\" -DDEFENV_VERILATOR_ROOT=\"/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator\" -c ../Verilator.cpp -o Verilator.o [...] g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -DDEFENV_SYSTEMC=\"\" -DDEFENV_SYSTEMC_ARCH=\"\" -DDEFENV_SYSTEMC_INCLUDE=\"\" -DDEFENV_SYSTEMC_LIBDIR=\"\" -DDEFENV_VERILATOR_ROOT=\"/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator\" -c ../V3WidthSel.cpp -o V3WidthSel.o Compile flags: g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -DDEFENV_SYSTEMC="" -DDEFENV_SYSTEMC_ARCH="" -DDEFENV_SYSTEMC_INCLUDE="" -DDEFENV_SYSTEMC_LIBDIR="" -DDEFENV_VERILATOR_ROOT="/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator" Linking ../../bin/verilator_bin_dbg... g++ -gz -static-libgcc -static-libstdc++ -Xlinker -gc-sections -o ../../bin/verilator_bin_dbg Verilator.o V3Active.o V3ActiveTop.o V3Assert.o V3AssertPre.o V3Ast.o V3AstNodes.o V3Begin.o V3Branch.o V3Broken.o V3CCtors.o V3CUse.o V3Case.o V3Cast.o V3Class.o V3Clean.o V3Clock.o V3Combine.o V3Common.o V3Config.o V3Const__gen.o V3Coverage.o V3CoverageJoin.o V3Dead.o V3Delayed.o V3Depth.o V3DepthBlock.o V3Descope.o V3Dfg.o V3DfgAstToDfg.o V3DfgDecomposition.o V3DfgDfgToAst.o V3DfgOptimizer.o V3DfgPasses.o V3DfgPeephole.o V3DupFinder.o V3EmitCBase.o V3EmitCConstPool.o V3EmitCFunc.o V3EmitCHeaders.o V3EmitCImp.o V3EmitCInlines.o V3EmitCMain.o V3EmitCMake.o V3EmitCModel.o V3EmitCSyms.o V3EmitMk.o V3EmitV.o V3EmitXml.o V3Error.o V3Expand.o V3File.o V3FileLine.o V3Force.o V3Gate.o V3Global.o V3Graph.o V3GraphAcyc.o V3GraphAlg.o V3GraphPathChecker.o V3GraphTest.o V3Hash.o V3Hasher.o V3HierBlock.o V3Inline.o V3Inst.o V3InstrCount.o V3Life.o V3LifePost.o V3LinkCells.o V3LinkDot.o V3LinkInc.o V3LinkJump.o V3LinkLValue.o V3LinkLevel.o V3LinkParse.o V3LinkResolve.o V3Localize.o V3MergeCond.o V3Name.o V3Number.o V3OptionParser.o V3Options.o V3Order.o V3Os.o V3Param.o V3ParseGrammar.o V3ParseImp.o V3ParseLex.o V3Partition.o V3PreProc.o V3PreShell.o V3Premit.o V3ProtectLib.o V3Randomize.o V3Reloop.o V3Sched.o V3SchedAcyclic.o V3SchedPartition.o V3SchedReplicate.o V3SchedTiming.o V3Scope.o V3Scoreboard.o V3Slice.o V3Split.o V3SplitAs.o V3SplitVar.o V3Stats.o V3StatsReport.o V3String.o V3Subst.o V3TSP.o V3Table.o V3Task.o V3ThreadPool.o V3Timing.o V3Trace.o V3TraceDecl.o V3Tristate.o V3Undriven.o V3Unknown.o V3Unroll.o V3VariableOrder.o V3Waiver.o V3Width.o V3WidthSel.o -lpthread -lm make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make[1]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src' ------------------------------------------------------------ making verilator in src make -C src make[1]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src' make -C obj_dbg -j 1 TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj serial make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make[2]: Nothing is done for 'serial'. make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make -C obj_dbg TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' Compile flags: g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -DDEFENV_SYSTEMC="" -DDEFENV_SYSTEMC_ARCH="" -DDEFENV_SYSTEMC_INCLUDE="" -DDEFENV_SYSTEMC_LIBDIR="" -DDEFENV_VERILATOR_ROOT="/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator" make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make -C obj_dbg TGT=../../bin/verilator_coverage_bin_dbg VL_DEBUG=1 VL_VLCOV=1 -f ../Makefile_obj serial_vlcov make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make[2]: Nothing is done for 'serial_vlcov'. make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make -C obj_dbg TGT=../../bin/verilator_coverage_bin_dbg VL_DEBUG=1 VL_VLCOV=1 -f ../Makefile_obj make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' Compile flags: g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -DDEFENV_SYSTEMC="" -DDEFENV_SYSTEMC_ARCH="" -DDEFENV_SYSTEMC_INCLUDE="" -DDEFENV_SYSTEMC_LIBDIR="" -DDEFENV_VERILATOR_ROOT="/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator" make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make -C obj_opt -j 1 TGT=../../bin/verilator_bin -f ../Makefile_obj serial make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_opt' make[2]: Nothing is done for 'serial'. make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_opt' make -C obj_opt TGT=../../bin/verilator_bin -f ../Makefile_obj make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_opt' Compile flags: g++ -O3 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -DDEFENV_SYSTEMC="" -DDEFENV_SYSTEMC_ARCH="" -DDEFENV_SYSTEMC_INCLUDE="" -DDEFENV_SYSTEMC_LIBDIR="" -DDEFENV_VERILATOR_ROOT="/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator" make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_opt' make[1]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src' help2man --no-info --no-discard-stderr --version-string=- bin/verilator_gantt -o verilator_gantt.1 make: help2man: File or directory does not exist make: *** [Makefile:191: verilator_gantt.1] Error 127 Installing Verilator in /home/username/Documentos/cva6Repo/tools/verilator-v5.008... ------------------------------------------------------------ making verilator in src make -C src make[1]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src' make -C obj_dbg -j 1 TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj serial make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make[2]: Nothing is done for 'serial'. make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make -C obj_dbg TGT=../../bin/verilator_bin_dbg VL_DEBUG=1 -f ../Makefile_obj make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' Compile flags: g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -DDEFENV_SYSTEMC="" -DDEFENV_SYSTEMC_ARCH="" -DDEFENV_SYSTEMC_INCLUDE="" -DDEFENV_SYSTEMC_LIBDIR="" -DDEFENV_VERILATOR_ROOT="/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator" make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make -C obj_dbg TGT=../../bin/verilator_coverage_bin_dbg VL_DEBUG=1 VL_VLCOV=1 -f ../Makefile_obj serial_vlcov make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make[2]: Nothing is done for 'serial_vlcov'. make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make -C obj_dbg TGT=../../bin/verilator_coverage_bin_dbg VL_DEBUG=1 VL_VLCOV=1 -f ../Makefile_obj make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' Compile flags: g++ -Og -ggdb -gz -DVL_DEBUG -D_GLIBCXX_DEBUG -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -DDEFENV_SYSTEMC="" -DDEFENV_SYSTEMC_ARCH="" -DDEFENV_SYSTEMC_INCLUDE="" -DDEFENV_SYSTEMC_LIBDIR="" -DDEFENV_VERILATOR_ROOT="/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator" make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_dbg' make -C obj_opt -j 1 TGT=../../bin/verilator_bin -f ../Makefile_obj serial make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_opt' make[2]: Nothing is done for 'serial'. make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_opt' make -C obj_opt TGT=../../bin/verilator_bin -f ../Makefile_obj make[2]: entering directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_opt' Compile flags: g++ -O3 -MMD -I. -I.. -I.. -I../../include -I../../include -MP -faligned-new -Wno-unused-parameter -Wno-shadow -DDEFENV_SYSTEMC="" -DDEFENV_SYSTEMC_ARCH="" -DDEFENV_SYSTEMC_INCLUDE="" -DDEFENV_SYSTEMC_LIBDIR="" -DDEFENV_VERILATOR_ROOT="/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator" make[2]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src/obj_opt' make[1]: leaving directory '/home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator/src' help2man --no-info --no-discard-stderr --version-string=- bin/verilator_gantt -o verilator_gantt.1 make: help2man: File or directory does not exist make: *** [Makefile:191: verilator_gantt.1] Error 127 /home/username/Documentos/cva6Repo Verilator version: Verilator 5.008 2023-03-04 rev v5.008 https://github.com/openhwgroup/cva6.git master 853fb4bee5ca6e36e39dc3c272a97f49d95c3c1d Building Spike sources in /home/username/Documentos/cva6Repo/verif/core-v-verif/vendor/riscv/riscv-isa-sim... make: *** No se especificó ningún objetivo y no se encontró ningún makefile. Alto. Installing Spike in '/home/username/Documentos/cva6Repo/tools/spike'... make: *** No hay ninguna regla para construir el objetivo 'install'. Alto. Defaulting to user installation because normal site-packages is not writeable Requirement already satisfied: PyYAML in /usr/lib/python3/dist-packages (from -r requirements.txt (line 1)) (5.4.1) Requirement already satisfied: bitstring in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 2)) (4.1.2) Requirement already satisfied: Sphinx in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 3)) (7.2.6) Requirement already satisfied: Pallets-Sphinx-Themes in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 4)) (2.1.1) Requirement already satisfied: sphinxcontrib-log-cabinet in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 5)) (1.0.1) Requirement already satisfied: sphinx-issues in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 6)) (3.0.1) Requirement already satisfied: sphinx_rtd_theme in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 7)) (1.3.0) Requirement already satisfied: rst2pdf in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 8)) (0.101) Requirement already satisfied: flake8 in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 9)) (6.1.0) Requirement already satisfied: pyvsc in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 10)) (0.8.6.6319294550) Requirement already satisfied: tabulate in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 11)) (0.9.0) Requirement already satisfied: pandas in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 12)) (2.1.3) Requirement already satisfied: bitarray<3.0.0,>=2.8.0 in /home/username/.local/lib/python3.10/site-packages (from bitstring->-r requirements.txt (line 2)) (2.8.3) Requirement already satisfied: sphinxcontrib-htmlhelp>=2.0.0 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (2.0.4) Requirement already satisfied: alabaster<0.8,>=0.7 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (0.7.13) Requirement already satisfied: packaging>=21.0 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (23.2) Requirement already satisfied: sphinxcontrib-qthelp in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (1.0.6) Requirement already satisfied: Jinja2>=3.0 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (3.1.2) Requirement already satisfied: sphinxcontrib-jsmath in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (1.0.1) Requirement already satisfied: Pygments>=2.14 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (2.16.1) Requirement already satisfied: sphinxcontrib-serializinghtml>=1.1.9 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (1.1.9) Requirement already satisfied: babel>=2.9 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (2.13.1) Requirement already satisfied: imagesize>=1.3 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (1.4.1) Requirement already satisfied: requests>=2.25.0 in /usr/lib/python3/dist-packages (from Sphinx->-r requirements.txt (line 3)) (2.25.1) Requirement already satisfied: sphinxcontrib-devhelp in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (1.0.5) Requirement already satisfied: snowballstemmer>=2.0 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (2.2.0) Requirement already satisfied: sphinxcontrib-applehelp in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (1.0.7) Requirement already satisfied: docutils<0.21,>=0.18.1 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (0.18.1) Requirement already satisfied: sphinxcontrib-jquery<5,>=4 in /home/username/.local/lib/python3.10/site-packages (from sphinx_rtd_theme->-r requirements.txt (line 7)) (4.1) Requirement already satisfied: reportlab in /usr/lib/python3/dist-packages (from rst2pdf->-r requirements.txt (line 8)) (3.6.8) Requirement already satisfied: smartypants in /home/username/.local/lib/python3.10/site-packages (from rst2pdf->-r requirements.txt (line 8)) (2.0.1) Requirement already satisfied: importlib-metadata in /usr/lib/python3/dist-packages (from rst2pdf->-r requirements.txt (line 8)) (4.6.4) Requirement already satisfied: mccabe<0.8.0,>=0.7.0 in /home/username/.local/lib/python3.10/site-packages (from flake8->-r requirements.txt (line 9)) (0.7.0) Requirement already satisfied: pycodestyle<2.12.0,>=2.11.0 in /home/username/.local/lib/python3.10/site-packages (from flake8->-r requirements.txt (line 9)) (2.11.1) Requirement already satisfied: pyflakes<3.2.0,>=3.1.0 in /home/username/.local/lib/python3.10/site-packages (from flake8->-r requirements.txt (line 9)) (3.1.0) Requirement already satisfied: pyucis>=0.1.0 in /home/username/.local/lib/python3.10/site-packages (from pyvsc->-r requirements.txt (line 10)) (0.1.2.2686817964) Requirement already satisfied: toposort in /home/username/.local/lib/python3.10/site-packages (from pyvsc->-r requirements.txt (line 10)) (1.10) Requirement already satisfied: pyboolector>=3.2.2 in /home/username/.local/lib/python3.10/site-packages (from pyvsc->-r requirements.txt (line 10)) (3.2.3.20231106.1) Requirement already satisfied: python-dateutil>=2.8.2 in /home/username/.local/lib/python3.10/site-packages (from pandas->-r requirements.txt (line 12)) (2.8.2) Requirement already satisfied: pytz>=2020.1 in /usr/lib/python3/dist-packages (from pandas->-r requirements.txt (line 12)) (2022.1) Requirement already satisfied: tzdata>=2022.1 in /home/username/.local/lib/python3.10/site-packages (from pandas->-r requirements.txt (line 12)) (2023.3) Requirement already satisfied: numpy<2,>=1.22.4 in /home/username/.local/lib/python3.10/site-packages (from pandas->-r requirements.txt (line 12)) (1.26.2) Requirement already satisfied: MarkupSafe>=2.0 in /usr/lib/python3/dist-packages (from Jinja2>=3.0->Sphinx->-r requirements.txt (line 3)) (2.0.1) Requirement already satisfied: six>=1.5 in /usr/lib/python3/dist-packages (from python-dateutil>=2.8.2->pandas->-r requirements.txt (line 12)) (1.16.0) Requirement already satisfied: jsonschema in /home/username/.local/lib/python3.10/site-packages (from pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (4.19.2) Requirement already satisfied: python-jsonschema-objects in /home/username/.local/lib/python3.10/site-packages (from pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (0.5.0) Requirement already satisfied: lxml in /home/username/.local/lib/python3.10/site-packages (from pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (4.9.3) Requirement already satisfied: attrs>=22.2.0 in /home/username/.local/lib/python3.10/site-packages (from jsonschema->pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (23.1.0) Requirement already satisfied: rpds-py>=0.7.1 in /home/username/.local/lib/python3.10/site-packages (from jsonschema->pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (0.12.0) Requirement already satisfied: jsonschema-specifications>=2023.03.6 in /home/username/.local/lib/python3.10/site-packages (from jsonschema->pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (2023.7.1) Requirement already satisfied: referencing>=0.28.4 in /home/username/.local/lib/python3.10/site-packages (from jsonschema->pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (0.30.2) Requirement already satisfied: Markdown>=2.4 in /home/username/.local/lib/python3.10/site-packages (from python-jsonschema-objects->pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (3.5.1) Requirement already satisfied: inflection>=0.2 in /home/username/.local/lib/python3.10/site-packages (from python-jsonschema-objects->pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (0.5.1) Repo: https://github.com/riscv-non-isa/riscv-arch-test.git Branch: main Hash: 220e78542da4510e40eac31e31fdd4e77cdae437 Patch: ../../../verif/regress/riscv-compliance.patch Repo: https://github.com/riscv/riscv-tests.git Branch: master Hash: f92842f91644092960ac7946a61ec2895e543cec Building Spike sources in /home/username/Documentos/cva6Repo/verif/core-v-verif/vendor/riscv/riscv-isa-sim... make: *** No se especificó ningún objetivo y no se encontró ningún makefile. Alto. Installing Spike in '/home/username/Documentos/cva6Repo/tools/spike'... make: *** No hay ninguna regla para construir el objetivo 'install'. Alto. Repo: https://github.com/riscv-non-isa/riscv-arch-test Branch: main Hash: a5a49fc9f244192649e57fe61b4513d9bc39b1e3 Wed, 15 Nov 2023 13:23:36 INFO GCC Version : 13.2.0 Wed, 15 Nov 2023 13:23:36 INFO Spike Version : /home/username/Documentos/cva6Repo/tools/spike Wed, 15 Nov 2023 13:23:36 INFO Verilator Version : Verilator 5.008 2023-03-04 rev v5.008 Wed, 15 Nov 2023 13:23:36 INFO Creating output directory: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15 Wed, 15 Nov 2023 13:23:36 INFO Execution numero : 1 Wed, 15 Nov 2023 13:23:36 INFO Processing regression test list : ../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml, test: rv64ui-v-add Wed, 15 Nov 2023 13:23:36 INFO Found matched tests: rv64ui-v-add, iterations:1 Wed, 15 Nov 2023 13:23:36 INFO CVA6 Configuration is Wed, 15 Nov 2023 13:23:36 INFO Compiling assembly test : /home/username/Documentos/cva6Repo/verif/tests/riscv-tests/isa/rv64ui/add.S /opt/riscv/lib/gcc/riscv64-unknown-elf/13.2.0/../../../../riscv64-unknown-elf/bin/ld: warning: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add.o has a LOAD segment with RWX permissions Wed, 15 Nov 2023 13:23:36 INFO Converting to /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add.bin Wed, 15 Nov 2023 13:23:36 INFO Processing ISS setup file : cva6.yaml Wed, 15 Nov 2023 13:23:36 INFO Found matching ISS: veri-testharness Wed, 15 Nov 2023 13:23:36 INFO ISA rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei Wed, 15 Nov 2023 13:23:36 INFO [veri-testharness] Running ISS simulation: make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add.log.iss Wed, 15 Nov 2023 13:23:37 INFO Wed, 15 Nov 2023 13:23:37 ERROR ERROR return code: True/2, cmd:make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add.log.iss Wed, 15 Nov 2023 13:23:37 INFO GCC Version : 13.2.0 Wed, 15 Nov 2023 13:23:37 INFO Spike Version : /home/username/Documentos/cva6Repo/tools/spike Wed, 15 Nov 2023 13:23:37 INFO Verilator Version : Verilator 5.008 2023-03-04 rev v5.008 Wed, 15 Nov 2023 13:23:37 INFO Creating output directory: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15 Wed, 15 Nov 2023 13:23:37 INFO Execution numero : 1 Wed, 15 Nov 2023 13:23:37 INFO Processing regression test list : ../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml, test: rv64ui-p-add Wed, 15 Nov 2023 13:23:37 INFO Found matched tests: rv64ui-p-add, iterations:1 Wed, 15 Nov 2023 13:23:37 INFO CVA6 Configuration is Wed, 15 Nov 2023 13:23:37 INFO Compiling assembly test : /home/username/Documentos/cva6Repo/verif/tests/riscv-tests/isa/rv64ui/add.S Wed, 15 Nov 2023 13:23:37 INFO Converting to /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add.bin Wed, 15 Nov 2023 13:23:37 INFO Processing ISS setup file : cva6.yaml Wed, 15 Nov 2023 13:23:37 INFO Found matching ISS: veri-testharness Wed, 15 Nov 2023 13:23:37 INFO ISA rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei Wed, 15 Nov 2023 13:23:37 INFO [veri-testharness] Running ISS simulation: make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add.log.iss Wed, 15 Nov 2023 13:23:38 INFO Wed, 15 Nov 2023 13:23:38 ERROR ERROR return code: True/2, cmd:make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add.log.iss Wed, 15 Nov 2023 13:23:38 INFO GCC Version : 13.2.0 Wed, 15 Nov 2023 13:23:38 INFO Spike Version : /home/username/Documentos/cva6Repo/tools/spike Wed, 15 Nov 2023 13:23:38 INFO Verilator Version : Verilator 5.008 2023-03-04 rev v5.008 Wed, 15 Nov 2023 13:23:38 INFO Creating output directory: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15 Wed, 15 Nov 2023 13:23:38 INFO Execution numero : 1 Wed, 15 Nov 2023 13:23:38 INFO Processing regression test list : ../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml, test: rv32i-I-ADD-01 Wed, 15 Nov 2023 13:23:38 INFO Found matched tests: rv32i-I-ADD-01, iterations:1 Wed, 15 Nov 2023 13:23:38 INFO CVA6 Configuration is Wed, 15 Nov 2023 13:23:38 INFO Compiling assembly test : /home/username/Documentos/cva6Repo/verif/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ADD-01.S Wed, 15 Nov 2023 13:23:38 INFO Converting to /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/I-ADD-01.bin Wed, 15 Nov 2023 13:23:38 INFO Processing ISS setup file : cva6.yaml Wed, 15 Nov 2023 13:23:38 INFO Found matching ISS: veri-testharness Wed, 15 Nov 2023 13:23:38 INFO ISA rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei Wed, 15 Nov 2023 13:23:38 INFO [veri-testharness] Running ISS simulation: make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/I-ADD-01.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/I-ADD-01.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/I-ADD-01.log.iss Wed, 15 Nov 2023 13:23:39 INFO Wed, 15 Nov 2023 13:23:39 ERROR ERROR return code: True/2, cmd:make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/I-ADD-01.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/I-ADD-01.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/I-ADD-01.log.iss Wed, 15 Nov 2023 13:23:39 INFO GCC Version : 13.2.0 Wed, 15 Nov 2023 13:23:39 INFO Spike Version : /home/username/Documentos/cva6Repo/tools/spike Wed, 15 Nov 2023 13:23:39 INFO Verilator Version : Verilator 5.008 2023-03-04 rev v5.008 Wed, 15 Nov 2023 13:23:39 INFO Creating output directory: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15 Wed, 15 Nov 2023 13:23:39 INFO Execution numero : 1 Wed, 15 Nov 2023 13:23:39 INFO Processing regression test list : ../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml, test: rv64i_m-add-01 Wed, 15 Nov 2023 13:23:39 INFO Found matched tests: rv64i_m-add-01, iterations:1 Wed, 15 Nov 2023 13:23:39 INFO CVA6 Configuration is Wed, 15 Nov 2023 13:23:39 INFO Compiling assembly test : /home/username/Documentos/cva6Repo/verif/tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/add-01.S Wed, 15 Nov 2023 13:23:40 INFO Converting to /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add-01.bin Wed, 15 Nov 2023 13:23:40 INFO Processing ISS setup file : cva6.yaml Wed, 15 Nov 2023 13:23:40 INFO Found matching ISS: veri-testharness Wed, 15 Nov 2023 13:23:40 INFO ISA rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei Wed, 15 Nov 2023 13:23:40 INFO [veri-testharness] Running ISS simulation: make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add-01.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add-01.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add-01.log.iss Wed, 15 Nov 2023 13:23:41 INFO Wed, 15 Nov 2023 13:23:41 ERROR ERROR return code: True/2, cmd:make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add-01.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add-01.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add-01.log.iss Wed, 15 Nov 2023 13:23:41 INFO GCC Version : 13.2.0 Wed, 15 Nov 2023 13:23:41 INFO Spike Version : /home/username/Documentos/cva6Repo/tools/spike Wed, 15 Nov 2023 13:23:41 INFO Verilator Version : Verilator 5.008 2023-03-04 rev v5.008 Wed, 15 Nov 2023 13:23:41 INFO Creating output directory: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15 Wed, 15 Nov 2023 13:23:41 INFO Execution numero : 1 Wed, 15 Nov 2023 13:23:41 INFO Processing regression test list : ../tests/testlist_custom.yaml, test: custom_test_template Wed, 15 Nov 2023 13:23:41 INFO Found matched tests: custom_test_template, iterations:1 Wed, 15 Nov 2023 13:23:41 INFO CVA6 Configuration is Wed, 15 Nov 2023 13:23:41 INFO Compiling assembly test : /home/username/Documentos/cva6Repo/verif/tests/custom/hello_world/custom_test_template.S /opt/riscv/lib/gcc/riscv64-unknown-elf/13.2.0/../../../../riscv64-unknown-elf/bin/ld: warning: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/custom_test_template.o has a LOAD segment with RWX permissions Wed, 15 Nov 2023 13:23:41 INFO Converting to /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/custom_test_template.bin Wed, 15 Nov 2023 13:23:41 INFO Processing ISS setup file : cva6.yaml Wed, 15 Nov 2023 13:23:41 INFO Found matching ISS: veri-testharness Wed, 15 Nov 2023 13:23:41 INFO ISA rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei Wed, 15 Nov 2023 13:23:41 INFO [veri-testharness] Running ISS simulation: make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/custom_test_template.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/custom_test_template.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/custom_test_template.log.iss Wed, 15 Nov 2023 13:23:42 INFO Wed, 15 Nov 2023 13:23:42 ERROR ERROR return code: True/2, cmd:make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/custom_test_template.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/custom_test_template.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/custom_test_template.log.iss Wed, 15 Nov 2023 13:23:42 INFO GCC Version : 13.2.0 Wed, 15 Nov 2023 13:23:42 INFO Spike Version : /home/username/Documentos/cva6Repo/tools/spike Wed, 15 Nov 2023 13:23:42 INFO Verilator Version : Verilator 5.008 2023-03-04 rev v5.008 Wed, 15 Nov 2023 13:23:42 INFO Creating output directory: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15 Wed, 15 Nov 2023 13:23:42 INFO Execution numero : 1 Wed, 15 Nov 2023 13:23:42 INFO Compiling c test : ../tests/custom/hello_world/hello_world.c Wed, 15 Nov 2023 13:23:42 INFO Converting to /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_c_tests/hello_world.bin Wed, 15 Nov 2023 13:23:42 INFO Processing ISS setup file : cva6.yaml Wed, 15 Nov 2023 13:23:42 INFO Found matching ISS: veri-testharness Wed, 15 Nov 2023 13:23:42 INFO ISA rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei Wed, 15 Nov 2023 13:23:42 INFO [veri-testharness] Running ISS simulation: make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_c_tests/hello_world.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/hello_world.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/hello_world.log.iss Wed, 15 Nov 2023 13:23:43 INFO Wed, 15 Nov 2023 13:23:43 ERROR ERROR return code: True/2, cmd:make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_c_tests/hello_world.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/hello_world.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/hello_world.log.iss make: entering directory '/home/username/Documentos/cva6Repo' Makefile:47: must set CVA6_REPO_DIR to point at the root of CVA6 sources -- doing it for you... Makefile:144: XCELIUM_HOME not set which is necessary for compiling DPIs when using XCELIUM rm -rf tmp/riscv-torture/output/test* rm -rf work/ work-dpi/ work-ver/ work-vcs/ rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* *.ucdb cd corev_apu/fpga && make clean && cd ../.. make[1]: entering directory '/home/username/Documentos/cva6Repo/corev_apu/fpga' rm -rf *.log *.jou *.str *.mif *.xpr work-fpga ariane.cache ariane.hw ariane.ip_user_files scripts/vivado* make[1]: leaving directory '/home/username/Documentos/cva6Repo/corev_apu/fpga' make: leaving directory '/home/username/Documentos/cva6Repo' Makefile:14: must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you... basename: falta un operando Pruebe 'basename --help' para más información. [VCS] Cleanup (entire vcs_work dir) rm -rf /home/username/Documentos/cva6Repo/verif/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart rm -f *.txt rm -f trace*.log rm -f trace*.dasm rm -f *.vpd *.fsdb *.vcd *.fst Wed, 15 Nov 2023 13:23:43 INFO GCC Version : 13.2.0 Wed, 15 Nov 2023 13:23:43 INFO Spike Version : /home/username/Documentos/cva6Repo/tools/spike Wed, 15 Nov 2023 13:23:43 INFO Verilator Version : Verilator 5.008 2023-03-04 rev v5.008 Wed, 15 Nov 2023 13:23:43 INFO Creating output directory: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15 Wed, 15 Nov 2023 13:23:43 INFO Execution numero : 1 Wed, 15 Nov 2023 13:23:43 INFO Processing regression test list : ../tests/testlist_riscv-compliance-cv32a60x.yaml, test: rv32i-I-ADD-01 Wed, 15 Nov 2023 13:23:43 INFO Found matched tests: rv32i-I-ADD-01, iterations:1 Wed, 15 Nov 2023 13:23:43 INFO CVA6 Configuration is Wed, 15 Nov 2023 13:23:43 INFO Compiling assembly test : /home/username/Documentos/cva6Repo/verif/tests/riscv-compliance/riscv-test-suite/rv32i/src/I-ADD-01.S Wed, 15 Nov 2023 13:23:43 INFO Converting to /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/I-ADD-01.bin Wed, 15 Nov 2023 13:23:43 INFO Processing ISS setup file : cva6.yaml Wed, 15 Nov 2023 13:23:43 INFO Found matching ISS: veri-testharness Wed, 15 Nov 2023 13:23:43 INFO ISA rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei Wed, 15 Nov 2023 13:23:43 INFO [veri-testharness] Running ISS simulation: make veri-testharness target=cv32a60x variant=rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/I-ADD-01.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/I-ADD-01.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/I-ADD-01.log.iss Wed, 15 Nov 2023 13:23:44 INFO Wed, 15 Nov 2023 13:23:44 ERROR ERROR return code: True/2, cmd:make veri-testharness target=cv32a60x variant=rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/I-ADD-01.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/I-ADD-01.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/I-ADD-01.log.iss Wed, 15 Nov 2023 13:23:44 INFO GCC Version : 13.2.0 Wed, 15 Nov 2023 13:23:44 INFO Spike Version : /home/username/Documentos/cva6Repo/tools/spike Wed, 15 Nov 2023 13:23:44 INFO Verilator Version : Verilator 5.008 2023-03-04 rev v5.008 Wed, 15 Nov 2023 13:23:44 INFO Creating output directory: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15 Wed, 15 Nov 2023 13:23:44 INFO Execution numero : 1 Wed, 15 Nov 2023 13:23:44 INFO Processing regression test list : ../tests/testlist_riscv-tests-cv32a60x-p.yaml, test: rv32ui-p-add Wed, 15 Nov 2023 13:23:44 INFO Found matched tests: rv32ui-p-add, iterations:1 Wed, 15 Nov 2023 13:23:44 INFO CVA6 Configuration is Wed, 15 Nov 2023 13:23:44 INFO Compiling assembly test : /home/username/Documentos/cva6Repo/verif/tests/riscv-tests/isa/rv32ui/add.S Wed, 15 Nov 2023 13:23:44 INFO Converting to /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add.bin Wed, 15 Nov 2023 13:23:44 INFO Processing ISS setup file : cva6.yaml Wed, 15 Nov 2023 13:23:44 INFO Found matching ISS: veri-testharness Wed, 15 Nov 2023 13:23:44 INFO ISA rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei Wed, 15 Nov 2023 13:23:44 INFO [veri-testharness] Running ISS simulation: make veri-testharness target=cv32a60x variant=rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add.log.iss Wed, 15 Nov 2023 13:23:45 INFO Wed, 15 Nov 2023 13:23:45 ERROR ERROR return code: True/2, cmd:make veri-testharness target=cv32a60x variant=rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/add.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/add.log.iss Wed, 15 Nov 2023 13:23:45 INFO GCC Version : 13.2.0 Wed, 15 Nov 2023 13:23:45 INFO Spike Version : /home/username/Documentos/cva6Repo/tools/spike Wed, 15 Nov 2023 13:23:45 INFO Verilator Version : Verilator 5.008 2023-03-04 rev v5.008 Wed, 15 Nov 2023 13:23:45 INFO Creating output directory: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15 Wed, 15 Nov 2023 13:23:45 INFO Execution numero : 1 Wed, 15 Nov 2023 13:23:45 INFO Processing regression test list : ../tests/testlist_riscv-arch-test-cv32a60x.yaml, test: rv32im-cadd-01 Wed, 15 Nov 2023 13:23:45 INFO Found matched tests: rv32im-cadd-01, iterations:1 Wed, 15 Nov 2023 13:23:45 INFO CVA6 Configuration is Wed, 15 Nov 2023 13:23:45 INFO Compiling assembly test : /home/username/Documentos/cva6Repo/verif/tests/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cadd-01.S Wed, 15 Nov 2023 13:23:45 INFO Converting to /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/cadd-01.bin Wed, 15 Nov 2023 13:23:45 INFO Processing ISS setup file : cva6.yaml Wed, 15 Nov 2023 13:23:45 INFO Found matching ISS: veri-testharness Wed, 15 Nov 2023 13:23:45 INFO ISA rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei Wed, 15 Nov 2023 13:23:45 INFO [veri-testharness] Running ISS simulation: make veri-testharness target=cv32a60x variant=rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/cadd-01.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/cadd-01.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/cadd-01.log.iss Wed, 15 Nov 2023 13:23:46 INFO Wed, 15 Nov 2023 13:23:46 ERROR ERROR return code: True/2, cmd:make veri-testharness target=cv32a60x variant=rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_asm_tests/cadd-01.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/cadd-01.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/veri-testharness_sim/cadd-01.log.iss Wed, 15 Nov 2023 13:23:46 INFO GCC Version : 13.2.0 Wed, 15 Nov 2023 13:23:46 INFO Spike Version : /home/username/Documentos/cva6Repo/tools/spike Wed, 15 Nov 2023 13:23:46 INFO Verilator Version : Verilator 5.008 2023-03-04 rev v5.008 Wed, 15 Nov 2023 13:23:46 INFO Creating output directory: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15 Wed, 15 Nov 2023 13:23:46 INFO Execution numero : 1 Wed, 15 Nov 2023 13:23:46 INFO Compiling c test : ../tests/custom/hello_world/hello_world.c Wed, 15 Nov 2023 13:23:46 INFO /opt/riscv/lib/gcc/riscv64-unknown-elf/13.2.0/../../../../riscv64-unknown-elf/bin/ld: /opt/riscv/lib/gcc/riscv64-unknown-elf/13.2.0/libgcc.a(div.o): ABI is incompatible with that of the selected emulation: target emulation `elf64-littleriscv' does not match `elf32-littleriscv' /opt/riscv/lib/gcc/riscv64-unknown-elf/13.2.0/../../../../riscv64-unknown-elf/bin/ld: falló la mezcla de datos específicos de objetivo del fichero /opt/riscv/lib/gcc/riscv64-unknown-elf/13.2.0/libgcc.a(div.o) /opt/riscv/lib/gcc/riscv64-unknown-elf/13.2.0/../../../../riscv64-unknown-elf/bin/ld: warning: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_c_tests/hello_world.o has a LOAD segment with RWX permissions /opt/riscv/lib/gcc/riscv64-unknown-elf/13.2.0/../../../../riscv64-unknown-elf/bin/ld: /tmp/ccQjC3Zo.o: en la función `verifyDouble': /home/username/Documentos/cva6Repo/verif/sim/../tests/custom/common/syscalls.c:36:(.text+0x186): undefined reference to `__eqdf2' /opt/riscv/lib/gcc/riscv64-unknown-elf/13.2.0/../../../../riscv64-unknown-elf/bin/ld: /home/username/Documentos/cva6Repo/verif/sim/../tests/custom/common/syscalls.c:36:(.text+0x1ae): undefined reference to `__eqdf2' /opt/riscv/lib/gcc/riscv64-unknown-elf/13.2.0/../../../../riscv64-unknown-elf/bin/ld: /home/username/Documentos/cva6Repo/verif/sim/../tests/custom/common/syscalls.c:39:(.text+0x23c): undefined reference to `__nedf2' collect2: error: ld returned 1 exit status Wed, 15 Nov 2023 13:23:46 ERROR ERROR return code: True/1, cmd:/opt/riscv/bin/riscv64-unknown-elf-gcc -mcmodel=medany -nostdlib -nostartfiles ../tests/custom/hello_world/hello_world.c -I/home/username/Documentos/cva6Repo/verif/sim/dv/user_extension -T../tests/custom/common/test.ld -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -lgcc -I../tests/custom/env -I../tests/custom/common -o /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-15/directed_c_tests/hello_world.o -march=rv32imac_zba_zbb_zbs_zbc_zicsr_zifencei -mabi=ilp32 make: entering directory '/home/username/Documentos/cva6Repo' Makefile:47: must set CVA6_REPO_DIR to point at the root of CVA6 sources -- doing it for you... Makefile:144: XCELIUM_HOME not set which is necessary for compiling DPIs when using XCELIUM rm -rf tmp/riscv-torture/output/test* rm -rf work/ work-dpi/ work-ver/ work-vcs/ rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* *.ucdb cd corev_apu/fpga && make clean && cd ../.. make[1]: entering directory '/home/username/Documentos/cva6Repo/corev_apu/fpga' rm -rf *.log *.jou *.str *.mif *.xpr work-fpga ariane.cache ariane.hw ariane.ip_user_files scripts/vivado* make[1]: leaving directory '/home/username/Documentos/cva6Repo/corev_apu/fpga' make: leaving directory '/home/username/Documentos/cva6Repo' Makefile:14: must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you... basename: one operand missing Try 'basename --help' for more information. [VCS] Cleanup (entire vcs_work dir) rm -rf /home/username/Documentos/cva6Repo/verif/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart rm -f *.txt rm -f trace*.log rm -f trace*.dasm rm -f *.vpd *.fsdb *.vcd *.fst /home/username/Documentos/cva6Repo ```

Thank you, I did not see that.

I installed help2man and ran: $ source verif/regress/dhrystone.sh

On the first run it seems to have compiled Verilator and it ended with this error:

ERROR    ERROR return code: True/2, cmd:make veri-testharness [...]

I ran it a second time, whose full log is below. It ended with the same error. Reding the output I noticed these lines but I don't know if it is the problem.

Makefile:14: must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you...
basename: missing an operand
Try 'basename --help' for more information.

Output:

``` username:cva6Repo$ source verif/regress/dhrystone.sh + source verif/regress/dhrystone.sh ++ '[' -n /opt/riscv ']' ++ source verif/regress/install-cva6.sh +++++ dirname verif/regress/install-cva6.sh ++++ readlink -f verif/regress/../../ +++ export ROOT_PROJECT=/home/username/Documentos/cva6Repo +++ ROOT_PROJECT=/home/username/Documentos/cva6Repo +++ export TOP=/home/username/Documentos/cva6Repo/tools +++ TOP=/home/username/Documentos/cva6Repo/tools +++ '[' -z /opt/riscv ']' +++ '[' -z riscv64-unknown-elf- ']' +++ '[' -z riscv64-unknown-elf-gcc ']' +++ '[' -z /opt/riscv/bin/riscv64-unknown-elf-objcopy ']' +++ export PATH=/opt/riscv/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/opt/riscv/bin:/tools/Xilinx/Vitis_HLS/2020.2/bin:/tools/Xilinx/Vivado/2020.2/bin:/tools/Xilinx/Model_Composer/2020.2/bin:/tools/Xilinx/Vitis/2020.2/bin:/tools/Xilinx/Vitis/2020.2/gnu/microblaze/lin/bin:/tools/Xilinx/Vitis/2020.2/gnu/arm/lin/bin:/tools/Xilinx/Vitis/2020.2/gnu/microblaze/linux_toolchain/lin64_le/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-none/bin:/tools/Xilinx/Vitis/2020.2/gnu/armr5/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.2/tps/lnx64/cmake-3.3.2/bin:/tools/Xilinx/Vitis/2020.2/aietools/bin:/tools/Xilinx/DocNav:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin:/tools:/opt/riscv/bin +++ PATH=/opt/riscv/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/opt/riscv/bin:/tools/Xilinx/Vitis_HLS/2020.2/bin:/tools/Xilinx/Vivado/2020.2/bin:/tools/Xilinx/Model_Composer/2020.2/bin:/tools/Xilinx/Vitis/2020.2/bin:/tools/Xilinx/Vitis/2020.2/gnu/microblaze/lin/bin:/tools/Xilinx/Vitis/2020.2/gnu/arm/lin/bin:/tools/Xilinx/Vitis/2020.2/gnu/microblaze/linux_toolchain/lin64_le/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-none/bin:/tools/Xilinx/Vitis/2020.2/gnu/armr5/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.2/tps/lnx64/cmake-3.3.2/bin:/tools/Xilinx/Vitis/2020.2/aietools/bin:/tools/Xilinx/DocNav:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin:/tools:/opt/riscv/bin +++ export LIBRARY_PATH=/opt/riscv/lib +++ LIBRARY_PATH=/opt/riscv/lib +++ export LD_LIBRARY_PATH=/opt/riscv/lib:/opt/riscv/lib: +++ LD_LIBRARY_PATH=/opt/riscv/lib:/opt/riscv/lib: +++ export C_INCLUDE_PATH=/opt/riscv/include +++ C_INCLUDE_PATH=/opt/riscv/include +++ export CPLUS_INCLUDE_PATH=/opt/riscv/include +++ CPLUS_INCLUDE_PATH=/opt/riscv/include +++ '[' /home/username/Documentos/cva6Repo/tools/verilator-v5.008 '!=' NO ']' +++ source verif/regress/install-verilator.sh ++++ '[' -z 24 ']' ++++ '[' -z /home/username/Documentos/cva6Repo/tools ']' ++++ VERILATOR_REPO=https://github.com/verilator/verilator.git ++++ VERILATOR_BRANCH=master ++++ VERILATOR_HASH=v5.008 ++++ VERILATOR_PATCH=/home/username/Documentos/cva6Repo/tools/../verif/regress/verilator-v5.patch ++++ '[' -n '' ']' ++++ '[' -z /home/username/Documentos/cva6Repo/tools/verilator-v5.008/verilator ']' ++++ '[' -z /home/username/Documentos/cva6Repo/tools/verilator-v5.008 ']' ++++ '[' '!' -f /home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin/verilator ']' ++++ echo 'Using Verilator from cached directory /home/username/Documentos/cva6Repo/tools/verilator-v5.008.' Using Verilator from cached directory /home/username/Documentos/cva6Repo/tools/verilator-v5.008. ++++ export PATH=/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/opt/riscv/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/opt/riscv/bin:/tools/Xilinx/Vitis_HLS/2020.2/bin:/tools/Xilinx/Vivado/2020.2/bin:/tools/Xilinx/Model_Composer/2020.2/bin:/tools/Xilinx/Vitis/2020.2/bin:/tools/Xilinx/Vitis/2020.2/gnu/microblaze/lin/bin:/tools/Xilinx/Vitis/2020.2/gnu/arm/lin/bin:/tools/Xilinx/Vitis/2020.2/gnu/microblaze/linux_toolchain/lin64_le/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-none/bin:/tools/Xilinx/Vitis/2020.2/gnu/armr5/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.2/tps/lnx64/cmake-3.3.2/bin:/tools/Xilinx/Vitis/2020.2/aietools/bin:/tools/Xilinx/DocNav:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin:/tools:/opt/riscv/bin ++++ PATH=/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/opt/riscv/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/opt/riscv/bin:/tools/Xilinx/Vitis_HLS/2020.2/bin:/tools/Xilinx/Vivado/2020.2/bin:/tools/Xilinx/Model_Composer/2020.2/bin:/tools/Xilinx/Vitis/2020.2/bin:/tools/Xilinx/Vitis/2020.2/gnu/microblaze/lin/bin:/tools/Xilinx/Vitis/2020.2/gnu/arm/lin/bin:/tools/Xilinx/Vitis/2020.2/gnu/microblaze/linux_toolchain/lin64_le/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-none/bin:/tools/Xilinx/Vitis/2020.2/gnu/armr5/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.2/tps/lnx64/cmake-3.3.2/bin:/tools/Xilinx/Vitis/2020.2/aietools/bin:/tools/Xilinx/DocNav:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin:/tools:/opt/riscv/bin +++ '[' -z /home/username/Documentos/cva6Repo/tools/verilator-v5.008 ']' +++ export PATH=/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/opt/riscv/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/opt/riscv/bin:/tools/Xilinx/Vitis_HLS/2020.2/bin:/tools/Xilinx/Vivado/2020.2/bin:/tools/Xilinx/Model_Composer/2020.2/bin:/tools/Xilinx/Vitis/2020.2/bin:/tools/Xilinx/Vitis/2020.2/gnu/microblaze/lin/bin:/tools/Xilinx/Vitis/2020.2/gnu/arm/lin/bin:/tools/Xilinx/Vitis/2020.2/gnu/microblaze/linux_toolchain/lin64_le/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-none/bin:/tools/Xilinx/Vitis/2020.2/gnu/armr5/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.2/tps/lnx64/cmake-3.3.2/bin:/tools/Xilinx/Vitis/2020.2/aietools/bin:/tools/Xilinx/DocNav:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin:/tools:/opt/riscv/bin +++ PATH=/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/opt/riscv/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/home/username/Documentos/cva6Repo/tools/verilator-v5.008/bin:/opt/riscv/bin:/tools/Xilinx/Vitis_HLS/2020.2/bin:/tools/Xilinx/Vivado/2020.2/bin:/tools/Xilinx/Model_Composer/2020.2/bin:/tools/Xilinx/Vitis/2020.2/bin:/tools/Xilinx/Vitis/2020.2/gnu/microblaze/lin/bin:/tools/Xilinx/Vitis/2020.2/gnu/arm/lin/bin:/tools/Xilinx/Vitis/2020.2/gnu/microblaze/linux_toolchain/lin64_le/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin:/tools/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-none/bin:/tools/Xilinx/Vitis/2020.2/gnu/armr5/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.2/tps/lnx64/cmake-3.3.2/bin:/tools/Xilinx/Vitis/2020.2/aietools/bin:/tools/Xilinx/DocNav:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin:/tools:/opt/riscv/bin +++ export C_INCLUDE_PATH=/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator/include:/opt/riscv/include +++ C_INCLUDE_PATH=/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator/include:/opt/riscv/include +++ export CPLUS_INCLUDE_PATH=/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator/include:/opt/riscv/include +++ CPLUS_INCLUDE_PATH=/home/username/Documentos/cva6Repo/tools/verilator-v5.008/share/verilator/include:/opt/riscv/include +++ echo 'Verilator version:' Verilator version: +++ verilator --version Verilator 5.008 2023-03-04 rev v5.008 +++ export NUM_JOBS=24 +++ NUM_JOBS=24 +++ '[' -z https://github.com/openhwgroup/cva6.git ']' +++ echo https://github.com/openhwgroup/cva6.git https://github.com/openhwgroup/cva6.git +++ echo master master +++ echo 853fb4bee5ca6e36e39dc3c272a97f49d95c3c1d 853fb4bee5ca6e36e39dc3c272a97f49d95c3c1d +++ echo +++ '[' -z /home/username/Documentos/cva6Repo/tools/spike ']' +++ source verif/regress/install-spike.sh ++++ '[' -z 24 ']' ++++ '[' -z /home/username/Documentos/cva6Repo ']' ++++ '[' -z /home/username/Documentos/cva6Repo/tools/spike ']' ++++ '[' /home/username/Documentos/cva6Repo/tools/spike = NO ']' ++++ '[' -z /home/username/Documentos/cva6Repo/verif/core-v-verif/vendor/riscv/riscv-isa-sim -o /home/username/Documentos/cva6Repo/tools/spike = __local__ ']' ++++ '[' -n /home/username/Documentos/cva6Repo/tools/spike -o /home/username/Documentos/cva6Repo/tools/spike = __local__ ']' ++++ export SPIKE_INSTALL_DIR=/home/username/Documentos/cva6Repo/tools/spike ++++ SPIKE_INSTALL_DIR=/home/username/Documentos/cva6Repo/tools/spike ++++ '[' -f /home/username/Documentos/cva6Repo/tools/spike/bin/spike ']' +++++ pwd ++++ CALLER_DIR=/home/username/Documentos/cva6Repo ++++ cd /home/username/Documentos/cva6Repo/verif/core-v-verif/vendor/riscv/riscv-isa-sim ++++ echo 'Building Spike sources in /home/username/Documentos/cva6Repo/verif/core-v-verif/vendor/riscv/riscv-isa-sim...' Building Spike sources in /home/username/Documentos/cva6Repo/verif/core-v-verif/vendor/riscv/riscv-isa-sim... ++++ mkdir -p build ++++ cd build ++++ [[ ! -f config.log ]] ++++ make -j24 make: *** No se especificó ningún objetivo y no se encontró ningún makefile. Alto. ++++ echo 'Installing Spike in '\''/home/username/Documentos/cva6Repo/tools/spike'\''...' Installing Spike in '/home/username/Documentos/cva6Repo/tools/spike'... ++++ make install make: *** No hay ninguna regla para construir el objetivo 'install'. Alto. ++++ cd /home/username/Documentos/cva6Repo ++ source verif/regress/install-riscv-dv.sh +++ export RISCV_TOOLCHAIN=/opt/riscv +++ RISCV_TOOLCHAIN=/opt/riscv +++ '[' -z riscv64-unknown-elf-gcc ']' +++ '[' -z /opt/riscv/bin/riscv64-unknown-elf-objcopy ']' +++ export SPIKE_PATH=/home/username/Documentos/cva6Repo/tools/spike/bin +++ SPIKE_PATH=/home/username/Documentos/cva6Repo/tools/spike/bin +++ export RTL_PATH=/home/username/Documentos/cva6Repo/ +++ RTL_PATH=/home/username/Documentos/cva6Repo/ +++ export TB_PATH=/home/username/Documentos/cva6Repo/verif/tb/core +++ TB_PATH=/home/username/Documentos/cva6Repo/verif/tb/core +++ export TESTS_PATH=/home/username/Documentos/cva6Repo/verif/tests +++ TESTS_PATH=/home/username/Documentos/cva6Repo/verif/tests +++ cd verif/sim/dv +++ pip3 install -r requirements.txt Defaulting to user installation because normal site-packages is not writeable Requirement already satisfied: PyYAML in /usr/lib/python3/dist-packages (from -r requirements.txt (line 1)) (5.4.1) Requirement already satisfied: bitstring in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 2)) (4.1.2) Requirement already satisfied: Sphinx in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 3)) (7.2.6) Requirement already satisfied: Pallets-Sphinx-Themes in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 4)) (2.1.1) Requirement already satisfied: sphinxcontrib-log-cabinet in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 5)) (1.0.1) Requirement already satisfied: sphinx-issues in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 6)) (3.0.1) Requirement already satisfied: sphinx_rtd_theme in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 7)) (1.3.0) Requirement already satisfied: rst2pdf in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 8)) (0.101) Requirement already satisfied: flake8 in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 9)) (6.1.0) Requirement already satisfied: pyvsc in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 10)) (0.8.6.6319294550) Requirement already satisfied: tabulate in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 11)) (0.9.0) Requirement already satisfied: pandas in /home/username/.local/lib/python3.10/site-packages (from -r requirements.txt (line 12)) (2.1.3) Requirement already satisfied: bitarray<3.0.0,>=2.8.0 in /home/username/.local/lib/python3.10/site-packages (from bitstring->-r requirements.txt (line 2)) (2.8.3) Requirement already satisfied: babel>=2.9 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (2.13.1) Requirement already satisfied: sphinxcontrib-jsmath in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (1.0.1) Requirement already satisfied: sphinxcontrib-applehelp in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (1.0.7) Requirement already satisfied: sphinxcontrib-htmlhelp>=2.0.0 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (2.0.4) Requirement already satisfied: sphinxcontrib-qthelp in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (1.0.6) Requirement already satisfied: Jinja2>=3.0 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (3.1.2) Requirement already satisfied: Pygments>=2.14 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (2.16.1) Requirement already satisfied: docutils<0.21,>=0.18.1 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (0.18.1) Requirement already satisfied: alabaster<0.8,>=0.7 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (0.7.13) Requirement already satisfied: sphinxcontrib-devhelp in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (1.0.5) Requirement already satisfied: imagesize>=1.3 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (1.4.1) Requirement already satisfied: requests>=2.25.0 in /usr/lib/python3/dist-packages (from Sphinx->-r requirements.txt (line 3)) (2.25.1) Requirement already satisfied: sphinxcontrib-serializinghtml>=1.1.9 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (1.1.9) Requirement already satisfied: snowballstemmer>=2.0 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (2.2.0) Requirement already satisfied: packaging>=21.0 in /home/username/.local/lib/python3.10/site-packages (from Sphinx->-r requirements.txt (line 3)) (23.2) Requirement already satisfied: sphinxcontrib-jquery<5,>=4 in /home/username/.local/lib/python3.10/site-packages (from sphinx_rtd_theme->-r requirements.txt (line 7)) (4.1) Requirement already satisfied: importlib-metadata in /usr/lib/python3/dist-packages (from rst2pdf->-r requirements.txt (line 8)) (4.6.4) Requirement already satisfied: reportlab in /usr/lib/python3/dist-packages (from rst2pdf->-r requirements.txt (line 8)) (3.6.8) Requirement already satisfied: smartypants in /home/username/.local/lib/python3.10/site-packages (from rst2pdf->-r requirements.txt (line 8)) (2.0.1) Requirement already satisfied: pycodestyle<2.12.0,>=2.11.0 in /home/username/.local/lib/python3.10/site-packages (from flake8->-r requirements.txt (line 9)) (2.11.1) Requirement already satisfied: mccabe<0.8.0,>=0.7.0 in /home/username/.local/lib/python3.10/site-packages (from flake8->-r requirements.txt (line 9)) (0.7.0) Requirement already satisfied: pyflakes<3.2.0,>=3.1.0 in /home/username/.local/lib/python3.10/site-packages (from flake8->-r requirements.txt (line 9)) (3.1.0) Requirement already satisfied: pyboolector>=3.2.2 in /home/username/.local/lib/python3.10/site-packages (from pyvsc->-r requirements.txt (line 10)) (3.2.3.20231106.1) Requirement already satisfied: toposort in /home/username/.local/lib/python3.10/site-packages (from pyvsc->-r requirements.txt (line 10)) (1.10) Requirement already satisfied: pyucis>=0.1.0 in /home/username/.local/lib/python3.10/site-packages (from pyvsc->-r requirements.txt (line 10)) (0.1.2.2686817964) Requirement already satisfied: numpy<2,>=1.22.4 in /home/username/.local/lib/python3.10/site-packages (from pandas->-r requirements.txt (line 12)) (1.26.2) Requirement already satisfied: tzdata>=2022.1 in /home/username/.local/lib/python3.10/site-packages (from pandas->-r requirements.txt (line 12)) (2023.3) Requirement already satisfied: python-dateutil>=2.8.2 in /home/username/.local/lib/python3.10/site-packages (from pandas->-r requirements.txt (line 12)) (2.8.2) Requirement already satisfied: pytz>=2020.1 in /usr/lib/python3/dist-packages (from pandas->-r requirements.txt (line 12)) (2022.1) Requirement already satisfied: MarkupSafe>=2.0 in /usr/lib/python3/dist-packages (from Jinja2>=3.0->Sphinx->-r requirements.txt (line 3)) (2.0.1) Requirement already satisfied: six>=1.5 in /usr/lib/python3/dist-packages (from python-dateutil>=2.8.2->pandas->-r requirements.txt (line 12)) (1.16.0) Requirement already satisfied: jsonschema in /home/username/.local/lib/python3.10/site-packages (from pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (4.19.2) Requirement already satisfied: lxml in /home/username/.local/lib/python3.10/site-packages (from pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (4.9.3) Requirement already satisfied: python-jsonschema-objects in /home/username/.local/lib/python3.10/site-packages (from pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (0.5.0) Requirement already satisfied: attrs>=22.2.0 in /home/username/.local/lib/python3.10/site-packages (from jsonschema->pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (23.1.0) Requirement already satisfied: jsonschema-specifications>=2023.03.6 in /home/username/.local/lib/python3.10/site-packages (from jsonschema->pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (2023.7.1) Requirement already satisfied: referencing>=0.28.4 in /home/username/.local/lib/python3.10/site-packages (from jsonschema->pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (0.30.2) Requirement already satisfied: rpds-py>=0.7.1 in /home/username/.local/lib/python3.10/site-packages (from jsonschema->pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (0.12.0) Requirement already satisfied: Markdown>=2.4 in /home/username/.local/lib/python3.10/site-packages (from python-jsonschema-objects->pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (3.5.1) Requirement already satisfied: inflection>=0.2 in /home/username/.local/lib/python3.10/site-packages (from python-jsonschema-objects->pyucis>=0.1.0->pyvsc->-r requirements.txt (line 10)) (0.5.1) ++ source verif/regress/install-riscv-compliance.sh +++ '[' -n https://github.com/riscv-non-isa/riscv-arch-test.git ']' +++ echo 'Repo: ' https://github.com/riscv-non-isa/riscv-arch-test.git Repo: https://github.com/riscv-non-isa/riscv-arch-test.git +++ echo Branch: main Branch: main +++ echo 'Hash: ' 220e78542da4510e40eac31e31fdd4e77cdae437 Hash: 220e78542da4510e40eac31e31fdd4e77cdae437 +++ echo 'Patch: ' ../../../verif/regress/riscv-compliance.patch Patch: ../../../verif/regress/riscv-compliance.patch +++ mkdir -p verif/tests +++ '[' -d verif/tests/riscv-compliance ']' ++ source verif/regress/install-riscv-tests.sh +++ '[' -n https://github.com/riscv/riscv-tests.git ']' +++ echo 'Repo: ' https://github.com/riscv/riscv-tests.git Repo: https://github.com/riscv/riscv-tests.git +++ echo Branch: master Branch: master +++ echo 'Hash: ' f92842f91644092960ac7946a61ec2895e543cec Hash: f92842f91644092960ac7946a61ec2895e543cec +++ mkdir -p verif/tests +++ '[' -d verif/tests/riscv-tests ']' ++ '[' -n veri-testharness ']' ++ make clean Makefile:47: must set CVA6_REPO_DIR to point at the root of CVA6 sources -- doing it for you... Makefile:144: XCELIUM_HOME not set which is necessary for compiling DPIs when using XCELIUM rm -rf tmp/riscv-torture/output/test* rm -rf work/ work-dpi/ work-ver/ work-vcs/ rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* *.ucdb cd corev_apu/fpga && make clean && cd ../.. make[1]: entering directory '/home/username/Documentos/cva6Repo/corev_apu/fpga' rm -rf *.log *.jou *.str *.mif *.xpr work-fpga ariane.cache ariane.hw ariane.ip_user_files scripts/vivado* make[1]: leaving directory '/home/username/Documentos/cva6Repo/corev_apu/fpga' ++ make -C verif/sim clean_all make: entering directory '/home/username/Documentos/cva6Repo/verif/sim' Makefile:14: must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you... basename: missing an operand Try 'basename --help' for more information. [VCS] Cleanup (entire vcs_work dir) rm -rf /home/username/Documentos/cva6Repo/verif/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart rm -f *.txt rm -f trace*.log rm -f trace*.dasm rm -f *.vpd *.fsdb *.vcd *.fst make: leaving directory '/home/username/Documentos/cva6Repo/verif/sim' ++ cd verif/sim ++ src0=../tests/riscv-tests/benchmarks/dhrystone/dhrystone_main.c ++ srcA=(../tests/riscv-tests/benchmarks/dhrystone/dhrystone.c ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S) ++ cflags=(-fno-tree-loop-distribute-patterns -nostdlib -nostartfiles -lgcc -O3 --no-inline -I../tests/custom/env -I../tests/custom/common -I../tests/riscv-tests/benchmarks/dhrystone/ -DNOPRINT) ++ set -x ++ python3 cva6.py --target hwconfig '--hwconfig_opts=--default_config=cv64a6_imafdc_sv39 --isa=rv64imafdc --NrLoadPipeRegs=0' --iss=veri-testharness --iss_yaml=cva6.yaml --c_tests ../tests/riscv-tests/benchmarks/dhrystone/dhrystone_main.c --gcc_opts '../tests/riscv-tests/benchmarks/dhrystone/dhrystone.c ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -fno-tree-loop-distribute-patterns -nostdlib -nostartfiles -lgcc -O3 --no-inline -I../tests/custom/env -I../tests/custom/common -I../tests/riscv-tests/benchmarks/dhrystone/ -DNOPRINT' --linker ../tests/custom/common/test.ld [Generating configuration ... ] Default configuration is cv64a6_imafdc_sv39 Make sure to compile your code with this ISA : rv64imafdc ! setting NrLoadPipeRegs to 0 setting HaltAddress to 2052 setting ExceptionAddress to 2056 WARNING: CVA6 configuration parameter 'CVA6ConfigZcbExtEn' not supported yet via cmdline args, consider extending script 'config_pkg_generator.py'! WARNING: CVA6 configuration parameter 'CVA6ConfigVExtEn' not supported yet via cmdline args, consider extending script 'config_pkg_generator.py'! WARNING: CVA6 configuration parameter 'CVA6ConfigZiCondExtEn' not supported yet via cmdline args, consider extending script 'config_pkg_generator.py'! [Generating configuration Done] Fri, 17 Nov 2023 13:34:30 INFO GCC Version : 13.2.0 Fri, 17 Nov 2023 13:34:30 INFO Spike Version : /home/username/Documentos/cva6Repo/tools/spike Fri, 17 Nov 2023 13:34:30 INFO Verilator Version : Verilator 5.008 2023-03-04 rev v5.008 Fri, 17 Nov 2023 13:34:30 INFO Creating output directory: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-17 Fri, 17 Nov 2023 13:34:30 INFO Execution numero : 1 Fri, 17 Nov 2023 13:34:30 INFO Compiling c test : ../tests/riscv-tests/benchmarks/dhrystone/dhrystone_main.c Fri, 17 Nov 2023 13:34:30 INFO Converting to /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-17/directed_c_tests/dhrystone_main.bin Fri, 17 Nov 2023 13:34:30 INFO Processing ISS setup file : cva6.yaml Fri, 17 Nov 2023 13:34:30 INFO Found matching ISS: veri-testharness Fri, 17 Nov 2023 13:34:30 INFO ISA rv64imafdc_zicsr_zifencei Fri, 17 Nov 2023 13:34:30 INFO [veri-testharness] Running ISS simulation: make veri-testharness target=gen64 variant=rv64imafdc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-17/directed_c_tests/dhrystone_main.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-17/veri-testharness_sim/dhrystone_main.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-17/veri-testharness_sim/dhrystone_main.log.iss Fri, 17 Nov 2023 13:34:52 INFO Fri, 17 Nov 2023 13:34:52 ERROR ERROR return code: True/2, cmd:make veri-testharness target=gen64 variant=rv64imafdc_zicsr_zifencei elf=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-17/directed_c_tests/dhrystone_main.o path_var=/home/username/Documentos/cva6Repo/ tool_path=/home/username/Documentos/cva6Repo/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1 +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/username/Documentos/cva6Repo/verif/sim/out_2023-11-17/veri-testharness_sim/dhrystone_main.log &> /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-17/veri-testharness_sim/dhrystone_main.log.iss ```

Log: /home/username/Documentos/cva6Repo/verif/sim/out_2023-11-17/veri-testharness_sim/dhrystone_main.log.iss

openhwgroup / cva6

Guidance to simulate CVA6 #1631