openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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uvme_cva6_cfg.sv uses hard constraints, prevents re-use by other CVA6 variants #1748

Open MikeOpenHWGroup opened 10 months ago

MikeOpenHWGroup commented 10 months ago

The uvme_cva6_cfg_c configuration class in cva6/verif/env/uvme/uvme_cva6_cfg.sv has a large set of hard constraints that set the values of cfg members. This means this cfg file is only usefull for one CVA6 variant, specifically the CV32A60X.

In order to make this configuration class reuseable, the hard constraints should either be removed (or set to "soft"), and the values of the members of uvme_cva6_cfg_c should be constrained in a variant-specific environment or testcase (the testcase is preferred).

This Issue is Labeled as both an "Enhancement" and a "Bug". For now, as we are only working on the CV32E60X, making this change is an enhancment, as it will not change functionality for a single variant. When we start supporting multiple variants of the CVA6, this Issue will become a bug.

MikeOpenHWGroup commented 10 months ago

Hi @AyoubJalali, I am assigning this issue to you since you have made several contributions to uvme_cva6_cfg.sv. Feel free to assign it to someone else if that is appropriate.

AyoubJalali commented 9 months ago

Hello @MikeOpenHWGroup , This one of our next steps of enhance the UVM CVA6 env, we want to make this env re-usable using the RTL configuration (CVA6Cfg), in this way when the RTL change or the configuration of the RTL the CVA6 env should change automatically, the work is ongoing.

AyoubJalali commented 3 months ago

@MikeOpenHWGroup could you check the uvme_cva6_cfg.sv, now it has values from the RTL configuration !