[BUG] *.dcp file does not exist for the DDR memory interface

[pcotret]

Is there an existing CVA6 bug for this?

• [X] I have searched the existing bug issues

Bug Description

I have an error while generating the FPGA bitstream:

make fpga

Gives me this error related to the MIG which should generate the DDR controller:

# set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "$registers"]]
# set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
# update_compile_order -fileset sources_1
# add_files -fileset constrs_1 -norecurse constraints/$project.xdc
# synth_design -rtl -name rtl_1
Command: synth_design -rtl -name rtl_1
Starting synth_design
Using part: xc7k325tffg900-2
Top: ariane_xilinx
INFO: [Device 21-403] Loading part xc7k325tffg900-2
1 Infos, 0 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Runs 36-527] DCP does not exist: /home/pascal/Documents/riscv-iommu-demo/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.dcp

The error is similar to https://github.com/openhwgroup/cva6/issues/824 but the solution given there didn't work (open ariane.xpr and generate output products for the DDR controller)

[pcotret]

Nevermind, it seemed to be an issue with my memory.