Condition coverage limitation

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

https://docs.openhwgroup.org/projects/cva6-user-manual/

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Condition coverage limitation #1902

Open JeanRochCoulon opened 8 months ago

JeanRochCoulon commented 8 months ago

Is there an existing CVA6 bug for this?

[X] I have searched the existing bug issues

Bug Description

In the frontend.sv, the line 373 does not appear in the condition coverage report. To me, this is a condition coverage case. I am concerned because I think it hides an implementation bug. How to make it appear in the coverage report?

@AyoubJalali @ASintzoff @AEzzejjari

AyoubJalali commented 8 months ago

Hello @JeanRochCoulon normally VCS can detect "?" condition by default, according to synopsys coverage manual :

also branch coverage don't detect this of course. So what a thing we should re-write the line to be visible for condition coverage

JeanRochCoulon commented 8 months ago

In the code, we have a = b ? c : d ; and not a <= b ? c : d ; That's maybe why it is not supported

AnouarZajni commented 8 months ago

Checked some condition coverage options but can't make the coverage, I think because it's a limitation while mixing "+" operand and expression. To make it work we need to split to 2 lines

AnouarZajni commented 7 months ago

Finaly, by splitting the line as following without any other condition coverage options the expression is covered:

AyoubJalali commented 7 months ago

@AnouarZajni Great !! But this is only an example, should we change in the hole design for that ? I don't think so

AnouarZajni commented 7 months ago

Yes I can see many similar expressions non-covered in design. You can find a non-exhaustive list in /shares/teams/riscv/fromAZ/missed_exp.txt @JeanRochCoulon , can you please review the list?