[Possible Issue] Instruction retire counters are incremented and updated simultaneously

[salaheddinhetalani]

Is there an existing CVA6 bug for this?

• [X] I have searched the existing bug issues

Bug Description

Instruction retire counters minstret and minstreth are incremented and updated (written by software) at the same time. Is this intended?

RISC-V Specification

Unprivileged ISA: 20191213 | Privileged Architecture: 20211203 | External Debug Support: 0.13.02

The minstret CSR counts the number of instructions the hart has retired. The mcycle and minstret registers have 64-bit precision on all RV32 and RV64 systems.

The counter registers have an arbitrary value after the hart is reset, and can be written with a given value. Any CSR write takes effect after the writing instruction has otherwise completed.

When MXLEN=32, reads of the mcycle, minstret, and mhpmcountern CSRs return bits 31–0 of the corresponding counter, and writes change only bits 31–0; reads of the mcycleh, minstreth, and mhpmcounternh CSRs return bits 63–32 of the corresponding counter, and writes change only bits 63–32.

Example Scenario

As shown below, the following sequence of instructions happens:

CSRRW x9, minstret, x9 -> CSRRC x0, minstret, x2

The instruction CSRRC x0, minstret, x2 is decoded at t_id and executed in machine mode resulting in updating the architecture state at t_arch_update. As a result, minstret is updated to have been incremented and then cleared at the same time.

Steps to Reproduce

Git Hash: de2e254c | TARGET_CFG: cv32a6_imac_sv0 | VCD: issue_17.zip

Component

Component:RTL

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Product: Questa OneSpin Solutions App: Questa Processor App Tool's version: 2024.1_1

[JeanRochCoulon]

Thanks @salaheddinhetalani for this study (all the bug issues opened these last days). The bug are very well linked to the specification. I am sure it will help the understanding. BTW, Today the Questasim tool is not fully supported by cva6 repo. Is there an interest from you in providing scripts to simulate with such tools ?

[salaheddinhetalani]

Hi @JeanRochCoulon, it's my pleasure. As for providing scripts to reproduce the issues reported using Questasim, I have already created SV testbenches based on the counterexamples of each issue. Would you be interested to have them shared here as well. Otherwise, the attached VCD files should be good enough to reproduce. Cheers!