openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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[AXI dv Plan]: Minor feedback #2065

Closed ludovicpion closed 5 months ago

ludovicpion commented 6 months ago

Is there an existing CVA6 bug for this?

Bug Description

Hi, As agreed, we (CEA) hae reviewed the AXI dv_plan. Only minor points to highlight.

Item: 013 • XLEN is not mentioned in the specification. Do we have to understand the XLEN= AXI DATA WIDTH ?

Item: 014 In the dvPlan: ARSIZE can not be equal to 3 if ARID = 1 but in the spec: if(RV32) ARSIZE != 3 && ARLEN = 0 && ARID = 1. => So the ARLEN = 0 condition is missing in the dvplan

In the dvPlan: ARSIZE can not be equal to 0, 1 or 2 if ARLOCK = 1 but in the spec if(RVA) AxLOCK = 1 => AxSIZE > 1. => Should be ARSIZE can not be equal to 0 or 1 if ARLOCK = 1 (already present in the Item: 015) ARSIZE is equal to 2 if ARLOCK = 1

Regards, Ludovic

JeanRochCoulon commented 6 months ago

Thank you @ludovicpion for this feedback

ludovicpion commented 6 months ago

Hi,

As far as I can see the comment on items 14 is still valid:

tem: 014 In the dvPlan: ARSIZE can not be equal to 3 if ARID = 1 but in the spec: if(RV32) ARSIZE != 3 && ARLEN = 0 && ARID = 1. => So the ARLEN = 0 condition is missing in the dvplan

In the dvPlan: ARSIZE can not be equal to 0, 1 or 2 if ARLOCK = 1 but in the spec if(RVA) AxLOCK = 1 => AxSIZE > 1. => Should be ARSIZE can not be equal to 0 or 1 if ARLOCK = 1 (already present in the Item: 015) ARSIZE is equal to 2 if ARLOCK = 1

Regards, Ludovic

JeanRochCoulon commented 5 months ago

@AEzzejjari Do you confirm the feedbacks are inserted in the doc ? If ok, the issue can be closed.

AEzzejjari commented 5 months ago

Yes I do