[BUG] <Test timeout when randomizing delay between AXI Write Address and Write Data>

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

https://docs.openhwgroup.org/projects/cva6-user-manual/

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[BUG] <Test timeout when randomizing delay between AXI Write Address and Write Data> #2075

Open AEzzejjari opened 2 months ago

AEzzejjari commented 2 months ago

Is there an existing CVA6 bug for this?

[X] I have searched the existing bug issues

Bug Description

Utilizing an updated AXI agent (PR #2416), a generated test timeout when randomizing the delay between AXI Write Address and Write Data, due to an issue with the RVFI. The RVFI fails to collect the correct physical address from the execute stage, preventing comparison with the TOHOST address and test completion.

Test name: riscv_load_store_hazard_test Seed: 1099370614

AEzzejjari commented 1 month ago

Just for info, the AXI agent does not randomize the ready-valid delay now. If you want to enable randomization, you can activate it in uvme_cva6_cfg.sv by setting axi_cfg.rand_channel_delay_enabled to 1.