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openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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Fix bug when killing WB cache request #2142

Closed cyprienh closed 4 months ago

cyprienh commented 4 months ago

This PR fixes a bug that could happen when a WB cache request gets killed while the _cachectrl is in the WAIT_REFILL_VALID state. When receiving the kill request, the _cachectrl went immediately back to the IDLE state. However, the AXI request was already issued and could be associated to the following cache request, effectively sending back the wrong data to the CPU. By not going immediately back to IDLE, the cache waits for the AXI response to arrive before going back to IDLE. Since this case is quite rare, the bottleneck introduced by not going immediately back to IDLE is minimal. The bug was found while running the WB TB. In this screenshot, the first request for addresss 0x10D1C gets killed and the cache_ctrl starts working on the next requets. image Later, the request for address 0x1D72 receives an AXI bypass response which is not the one it was supposed to receive but associates it with the current cache request: image Which causes the bug: image

JeanRochCoulon commented 4 months ago

@niwis Can you approve the PR ?

github-actions[bot] commented 4 months ago

:heavy_check_mark: successful run, report available here.

github-actions[bot] commented 4 months ago

:heavy_check_mark: successful run, report available here.

github-actions[bot] commented 4 months ago

:heavy_check_mark: successful run, report available here.