[BUG] Cacheable regions PMA attribute not compatible with AXI memory type signal

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

https://docs.openhwgroup.org/projects/cva6-user-manual/

Other

2.15k stars 652 forks source link

[BUG] Cacheable regions PMA attribute not compatible with AXI memory type signal #2143

Open abdelhak-chkirid opened 1 month ago

abdelhak-chkirid commented 1 month ago

Is there an existing CVA6 bug for this?

[X] I have searched the existing bug issues

Bug Description

Illegal memory access to the cacheable region (8000_0000 <= address <= c000_0000) due to a mismatch between the AXI bus and the PMA rules. The ARCACHE signal in the AXI interface indicates that the memory type is NonCacheable, but the PMA is configured as cacheable in this memory region.