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openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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[UVM TB] Initialize information about DRAM presence, address and size. #2153

Closed zchamski closed 1 month ago

zchamski commented 1 month ago

Fxx issue openhwgroup/core-v-verif#2444: Fill the 'dram', 'dram_base' and 'dram_size' fields of the st_core_cntrl_cfg structure with reliable values.

The corresponding fields in the (virtual) base class of st_core_cntrl_cfg are declared with 'rand' modifier. In particular, the 'dram' field could occasionally take value 1'b1, causing the Spike tandem interface to pass the random values of DRAM base address and DRAM size to Spike. When DRAM size is not a strictly positive multiple of PAGE_SIZE, Spike throws a runtime exception causing issue openhwgroup/core-v-verif#2444.

NOTE: The comment added in the code is there purposely as a reminder that we need an overhaul of memory layout management.

github-actions[bot] commented 1 month ago

:heavy_check_mark: successful run, report available here.