Complete the CSR documentation

[JeanRochCoulon]

Bug Description

Analyzing the differences between the riscv-config.yaml, CSR.rst from IP-XACT and CSR.rst from Riscv-config, these improvments need to be done:

• Add legal values (0x0, 0x3) in final CSR documentation.
• What is mask value ?
• Replace RW by WARL. Indeed the CSR is read/write, but the field is WARL.
• Add the reset value

riscv-config.yaml :

IP-XACT :

Riscv-config :

[JeanRochCoulon]

@AbdessamiiOukalrazqou @AnouarZajni

[JeanRochCoulon]

@ASintzoff

[zchamski]

A couple observations:

• If we consider CV32A65X, there is no user mode so the only valid "previous" mode is M (0x3) ==> both specs are wrong;
• capitalization of field names is a rendering action ==> can/should be done in gen_from_riscv_config;
• the short title/heading ("Machine mode prior privilege") is a feature to be added to RVconfig or to the updater;
• the list of value meanings [("U-mode" :0 ) etc.] have to be added either to the spec or to RVconfig ==> to be explored.

[JeanRochCoulon]

Feedback about MSTATUS CSR from this morning discussion:

• XS is wrong in rt file: isa_gen.yaml file need to be re-generated by @zchamski
• UBE need to be added in isa.yaml by @zchamski
• SPELP newly added in Riscv international specification, to be better documented in riscv specification by @ASintzoff
• RO to be replaced by WARL by @zchamski

[JeanRochCoulon]

Additional feedback:

• All vacant field need to be added to the rst file, the related type is "WPRI" (and not RESERVED), @AbdessamiiOukalrazqou

[JeanRochCoulon]

2187 solved this issue. Thank @AbdessamiiOukalrazqou