search

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
Other
2.23k stars 677 forks source link

Disable MISA WE in Reference Model #2181

Closed MarioOpenHWGroup closed 4 months ago

MarioOpenHWGroup commented 4 months ago
JeanRochCoulon commented 4 months ago

@zchamski Can you approve ?

AyoubJalali commented 4 months ago

I don't know why but I need to give the cva6.py the misa_we_enabled to get spike work !!

JeanRochCoulon commented 4 months ago

MISA is read only. I do not understand why in Spike MISA need to be write-able !? misa_we_enable =1

image

zchamski commented 4 months ago

I don't know why but I need to give the cva6.py the misa_we_enabled to get spike work !!

The misa_we_enable parameter (with value 'true') enables the control of the writability of MISA via the parameter misa_we. If misa_we_enable is left at false, the default behavior of Spike remains in effect, which is to keep MISA extension bits MAFDQCHV writable (https://github.com/openhwgroup/core-v-verif/blob/master/vendor/riscv/riscv-isa-sim/riscv/csrs.cc#L613)

github-actions[bot] commented 4 months ago

:heavy_check_mark: successful run, report available here.