CSR spec improvements

[JeanRochCoulon]

Feedback on the CSR specification https://github.com/openhwgroup/cva6/blob/master/config/gen_from_riscv_config/cv32a65x/csr/csr.rst

• Replace the WARL with only one value by ROCST (RO constant). Will be done in input specification @zchamski.

• Use ROVAR (RO variable) when a RO value can be modified by hardware. Need for the tests.

• Before the register Summary, remind the definition of WARL, WLRL, WPRI, ROCST, ROVAR. Will be done by @zchamski.

• In Register Summary, add a column in the table to provide the access type : RW/RO

• In Register Description, add the access type before the table : RW/RO

• Move the "Legal Values" column between "Type" and "Description" columns

• Replace "RESERVED" from Description column by "Reserved". See Table 10 in priv specification.

• In MISA, can you expand the EXTENSIONS field ?

[JeanRochCoulon]

@AbdessamiiOukalrazqou @zchamski @AnouarZajni

[AnouarZajni]

@JeanRochCoulon , I think you are referring to https://github.com/openhwgroup/cva6/blob/master/config/gen_from_riscv_config/cv32a65x/csr/csr.rst ?

[JeanRochCoulon]

The above modifications has been implemented in the CSR specification. The PR can be closed.