[Xcelium flow] corev dv yaml

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

https://docs.openhwgroup.org/projects/cva6-user-manual/

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[Xcelium flow] corev dv yaml #2210

Closed CoralieAllioux closed 3 weeks ago

CoralieAllioux commented 3 weeks ago

This PR aims at adding xrun rule in verif/env/corev-dv/simulator.yaml, which is a step to support Cadence xcelium simulator while using riscv-dv instruction generator. It contributes to task #1829

github-actions[bot] commented 3 weeks ago

:heavy_check_mark: successful run, report available here.

github-actions[bot] commented 3 weeks ago

:heavy_check_mark: successful run, report available here.