Closed CoralieAllioux closed 3 weeks ago
This PR aims at adding xrun rule inverif/sim/cva6.yaml, which is a step to support Cadence xcelium simulator without using riscv-dv instruction generator. It contributes to task #1829
verif/sim/cva6.yaml
:heavy_check_mark: successful run, report available here.
This PR aims at adding xrun rule in
verif/sim/cva6.yaml
, which is a step to support Cadence xcelium simulator without using riscv-dv instruction generator. It contributes to task #1829