[Xcelium flow] xrun uvm rules

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

https://docs.openhwgroup.org/projects/cva6-user-manual/

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[Xcelium flow] xrun uvm rules #2224

Closed CoralieAllioux closed 3 weeks ago

CoralieAllioux commented 3 weeks ago

This PR aims at updating the rules into cva6/verif/sim/Makefile to support uvmt_cva6_tb (in cva6/verif/tb/uvmt) on Cadence Xcelium. Nevertheless, this PR is not enough to launch cva6.py with _xrun_uvm DVSIMULATOR. Further PRs will follow.

It contributes to task https://github.com/openhwgroup/cva6/issues/1829

github-actions[bot] commented 3 weeks ago

:heavy_check_mark: successful run, report available here.