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openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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[BUG] : mstatus.TW is set to 1 #2228

Closed AyoubJalali closed 3 months ago

AyoubJalali commented 3 months ago

Is there an existing CVA6 bug for this?

Bug Description

Hello, the cv32a65x spec the TW filed in MSTATUS is read-only zero, but the RTL allow the read 1 in TW filed after a write into it :

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