[BUG] SPIKE model is not configurable with TvalEn core option

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

https://docs.openhwgroup.org/projects/cva6-user-manual/

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[BUG] SPIKE model is not configurable with TvalEn core option #2243

Open LQUA opened 2 weeks ago

LQUA commented 2 weeks ago

Is there an existing CVA6 bug for this?

[X] I have searched the existing bug issues

Bug Description

CV32A65X core has its TvalEn option set to 0. The following tests are failed :

rv32mi-ma_addr
rv32i-I-MISALIGN_LDST-01

The failure is due to the mtval value after the exception : the core set mtval to 0 (due to TvalEn) when SPIKE model is expecting the trapping address

In 64 bit configurations with TvalEn set to 0, rv64mi-p-ma_addr is also failed

This issue is linked to #1403

zchamski commented 2 weeks ago

This is a duplicate of https://github.com/openhwgroup/core-v-verif/issues/2468. Since the issue is on Spike side, it will be handled under https://github.com/openhwgroup/core-v-verif/.