[riscv-config] Update riscv-config tool, CV32A65X specs and the rendering of CSRs. - Githubissues

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

https://docs.openhwgroup.org/projects/cva6-user-manual/

Other

2.14k stars 652 forks source link

[riscv-config] Update riscv-config tool, CV32A65X specs and the rendering of CSRs. #2270

Closed zchamski closed 1 week ago

zchamski commented 1 week ago

Fix issues in riscv-config:

incorrect address of MSTATUSH
non-standard characters in MSTATUS/MSTATUSH descriptions
add minssing schema for MCONFIGPTR
add corresponding patches.

Update riscv-config spec of CV32A65X:

mark MCOUNTINHIBIT as not implemented
add MCONFIGPTR (RO zero)
allow full range of values for MVTEC.BASE.

gen_from_riscv_config:

use register address to determine RO/RW access privilege
improve rendering of ranges, bitmasks and value sets