Closed JeanRochCoulon closed 2 months ago
Taking the points in order:
exception information need to be added: when exception will be generated ?
riscv-config
does not support per-CSR exception information, the requested "exception information" will most likely take the form of an additional paragraph in the introduction of the CSR design doc (@zchamski)Upper PMP CSR are ROCST zero
PMPADDRn
registers with n = 8-15
? The definitions of these registers are ROCST zero in the riscv-config
spec but they are later folded into a generic definition in the CSR factorizer. I will have a look at the code and ask @AbdessamiiOukalrazqou for help if needed.PMPCfg have several bits stuck at zero
riscv-config
input spec (@zchamski) and handled in the CSR factorizer (@zchamski with support from @AbdessamiiOukalrazqou). In the rv-config input spec there are two tasks:
PMPCONFIG0
/PMPCONFIG1
need to be made explicit by maskingMCONFIGPTR does not exist
riscv-config
input spec, in the rendered CSR design doc and in the RTL.replace MHPMCOUNTER[]H by MHPMCOUNTERH[]
H
suffix is placed after the number. Maybe the interval notation ("firsteg - lastreg") and properly typeset names such as MHPMCOUNTERnH will be a better solution (but RST is limited in this respect.)in CSR list, replace []_ by []
In legal value, replace "0 - 1" by "0x0 - 0x1"
I agree about MCONFIGPTR, this CSR exists. And I am ok to keep MHPMCOUNTERH as it is Today.
This issue has been fixed in CSR specification, thanks @AbdessamiiOukalrazqou
Several feedbacks from 65x CSR document https://docs.openhwgroup.org/projects/cva6-user-manual/04_cv32a65x/design/source/CSRs.html