openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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[TASK] Implement CVXIF 1.0.0 instruction dedicated to verification #2277

Open Gchauvon opened 3 months ago

Gchauvon commented 3 months ago

Is there an existing CVA6 task for this?

Task Description

To ensure a good verification of the CVXIF 1.0.0 implementation for CVA6, it is necessary to define instructions to challenge all the features of the specification.

A good draft of the required instruction are defined in the uploaded file. Those instructions will be implemented in the CVXIF example coprocessor and connected to the CVA6 with an updated version of the CVXIF.

It is necessary to update Spike aswell to match RTL and Spike in dedicated tests for non-regression and verification purposes.

custom_instructions_cvxif_1_0_0.txt

Required Changes

Update of the cvxif.cc file in Spike to support all described instructions. Support of custom instruction in place of MADD, NMADD, MSUB, NMSUBwhen F extension is disable. Support of RS3 in place of RD in some CVXIF instructions. Support of compressed CVXIF instruction in place of compressed floating point instruction when F extension is disable.

Current Status

A deprecated version of CVXIF 0.2.0 in Spike existed. It needs to be updated.

Risks

No response

Prerequisites

No response

KPI (KEY Performance Indicators)

No response

Description of Done

All described instructions are implemented in Spike and functional when F extension is disable.

Associated PRs

No response