search

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
Other
2.14k stars 652 forks source link

[BUG] B extension: incorrect decoding for some instructions in RV32 #2280

Open ASintzoff opened 1 week ago

ASintzoff commented 1 week ago

Is there an existing CVA6 bug for this?

Bug Description

According to RISC-V ISA specification, for RV32, the bit 25 of instructions BCLRI, BINVI, BSETI, BEXTI and RORI must be equal to zero. So when this bit is set, an illegal instruction exception has to be raised.

With the current implementation, when bit 25 is set, there is no exception for RV32.

end else if (instr.instr[31:26] == 6'b010010) instruction_o.op = ariane_pkg::BCLRI;
                else if (instr.instr[31:26] == 6'b011010) instruction_o.op = ariane_pkg::BINVI;
                else if (instr.instr[31:26] == 6'b001010) instruction_o.op = ariane_pkg::BSETI;
                else illegal_instr_bm = 1'b1;
  else if (instr.instr[31:26] == 6'b010_010) instruction_o.op = ariane_pkg::BEXTI;
                else if (instr.instr[31:26] == 6'b011_000) instruction_o.op = ariane_pkg::RORI;
                else illegal_instr_bm = 1'b1;
JeanRochCoulon commented 1 week ago

I agree with the Github issue, but which specification tells us that an exception is raised when bit25 is equal to zero ?

AyoubJalali commented 1 week ago

I agree with the Github issue, but which specification tells us that an exception is raised when bit25 is equal to zero ?

if the 25th bit isn't equal to zero these instruction are treated as RV64 instruction base on the RISCV bitmanip spec