[BUG] stall_instr_fetch signal in core/id_stage.sv will not be driven if CVA6Cfg.RVZCMP is disabled

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

https://docs.openhwgroup.org/projects/cva6-user-manual/

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[BUG] stall_instr_fetch signal in core/id_stage.sv will not be driven if CVA6Cfg.RVZCMP is disabled #2289

Open ckf104 opened 1 week ago

ckf104 commented 1 week ago

Is there an existing CVA6 bug for this?

[X] I have searched the existing bug issues

Bug Description

stall_instr_fetch signal in core/id_stage.sv will not be driven if CVA6Cfg.RVZCMP is disabled. When using simulator like verilator with random initial value, cva6 may be stalled all the time.