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openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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Error while running riscv-arch-test #2290

Open abhikutari opened 6 days ago

abhikutari commented 6 days ago

Hello,

We are trying to run the regression for test: dv-risv-arch-test.sh with DV_TARGET=cv32a6_imac_sv32 DV_SIMULATORS=vcs-uvm,spike TESTLIST=../tests/testlist_riscv-arch-test-cv32a60x.yaml all the test cases are running correctly and matched, after this running the regression we got Error for Source "riscv_core_setting.sv" cannot be opened which is in riscv_instr_pkg.sv:

  Mon, 24 Jun 2024 03:18:51 INFO     Processing simulator setup file: /cva6_verif/verif/sim/cva6-simulator.yaml   Mon, 24 Jun 2024 03:18:51 INFO     Found matching simulator: vcs   Mon, 24 Jun 2024 03:18:51 INFO     Building RISC-V instruction generator   Mon, 24 Jun 2024 03:18:54 INFO     Chronologic VCS (TM)   Error-[SFCOR] Source file cannot be opened Source file "riscv_core_setting.sv" cannot be opened for reading due to 'No such file or directory'. Please fix above issue and compile again. "/cva6_verif/verif/sim/dv/src/riscv_instr_pkg.sv", line no: 1213 Source info: `include "riscv_core_setting.sv"

we have commented coverage swith from makefile but still i'm getting this error

any suggestions to fix this issue in riscv-arch-testlist

Thanks

JeanRochCoulon commented 6 days ago

@valentinThomazic