I am desperately trying to get CVA6 running on my Genesys II board; however, I am facing multiple challenges. Some of these might be due to the fact that I haven't worked with FPGAs since university 10 years ago. :-) I hope someone can point me in the right direction.
Inability to Generate Bitstream
I am encountering several challenges. Firstly, when I attempt to generate the bitstream myself, I get errors. I followed the guide, installed Vivado and the toolchain, and added the bin directory to my path. However, when running make fpga, it runs for 6-7 minutes and then fails with errors during synthesis. I logged the output here: Part 1, Part 2, and Part 3.
Short version:
ERROR: [Synth 8-524] part-select [15:0] out of range of prefix 'rs2_forwarding_i' [/home/bonne/Documents/test/cva6/core/ex_stage.sv:625] ERROR: [Synth 8-6156] failed synthesizing module 'ex_stage' [/home/bonne/Documents/test/cva6/core/ex_stage.sv:17] ERROR: [Synth 8-6156] failed synthesizing module 'cva6' [/home/bonne/Documents/test/cva6/core/cva6.sv:17] ERROR: [Synth 8-6156] failed synthesizing module 'ariane' [/home/bonne/Documents/test/cva6/corev_apu/src/ariane.sv:16] ERROR: [Synth 8-6156] failed synthesizing module 'ariane_xilinx' [/home/bonne/Documents/test/cva6/corev_apu/fpga/src/ariane_xilinx.sv:14] ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details make[1]: *** [Makefile:28: work-fpga/ariane_xilinx.bit] Error 1 make: *** [Makefile:739: fpga] Error 2
I've tried reinstalling Vivado, reinstalling the toolchain, re-pulling CVA6, even got more RAM - no progress.
Missing Memory Configuration Files
While I am not entirely sure of the difference between bitstreams and memory configuration files, I would expect that both are required. However, under the precompiled files, I can only see bitstreams in the newest version. Is this because the older versions should be used?
Unable to Boot from Memory Configuration
I asked my colleague, who was able to generate the .mcs and .bit files, to send them to me. I set my Genesys II in JTAG mode and opened Vivado. I can see my device under the hardware manager, which is great. According to the guide, I should select the following Spansion SPI flash: s25fl256xxxxxx0. However, I only see s25fl256sxxxxxx0 (with an 's'). Is this a typo, or why don't I see the correct one?
Regardless, I continued by selecting my .mcs file and started programming. This takes a few minutes and seems to work fine. Then, following the guide, I selected "Boot from Configuration Memory Device." This process continues for a few minutes but fails at 100% with a generic error, as seen in the log here.
My apologies if this is not the right place to ask, but can anyone point me in the right direction to successfully run CVA6 on my Genesys II?
I am desperately trying to get CVA6 running on my Genesys II board; however, I am facing multiple challenges. Some of these might be due to the fact that I haven't worked with FPGAs since university 10 years ago. :-) I hope someone can point me in the right direction.
Inability to Generate Bitstream I am encountering several challenges. Firstly, when I attempt to generate the bitstream myself, I get errors. I followed the guide, installed Vivado and the toolchain, and added the bin directory to my path. However, when running
make fpga, it runs for 6-7 minutes and then fails with errors during synthesis. I logged the output here: Part 1, Part 2, and Part 3.Short version:
ERROR: [Synth 8-524] part-select [15:0] out of range of prefix 'rs2_forwarding_i' [/home/bonne/Documents/test/cva6/core/ex_stage.sv:625] ERROR: [Synth 8-6156] failed synthesizing module 'ex_stage' [/home/bonne/Documents/test/cva6/core/ex_stage.sv:17] ERROR: [Synth 8-6156] failed synthesizing module 'cva6' [/home/bonne/Documents/test/cva6/core/cva6.sv:17] ERROR: [Synth 8-6156] failed synthesizing module 'ariane' [/home/bonne/Documents/test/cva6/corev_apu/src/ariane.sv:16] ERROR: [Synth 8-6156] failed synthesizing module 'ariane_xilinx' [/home/bonne/Documents/test/cva6/corev_apu/fpga/src/ariane_xilinx.sv:14] ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details make[1]: *** [Makefile:28: work-fpga/ariane_xilinx.bit] Error 1 make: *** [Makefile:739: fpga] Error 2I've tried reinstalling Vivado, reinstalling the toolchain, re-pulling CVA6, even got more RAM - no progress.
Missing Memory Configuration Files While I am not entirely sure of the difference between bitstreams and memory configuration files, I would expect that both are required. However, under the precompiled files, I can only see bitstreams in the newest version. Is this because the older versions should be used?
Unable to Boot from Memory Configuration I asked my colleague, who was able to generate the .mcs and .bit files, to send them to me. I set my Genesys II in JTAG mode and opened Vivado. I can see my device under the hardware manager, which is great. According to the guide, I should select the following Spansion SPI flash: s25fl256xxxxxx0. However, I only see s25fl256sxxxxxx0 (with an 's'). Is this a typo, or why don't I see the correct one?
Regardless, I continued by selecting my .mcs file and started programming. This takes a few minutes and seems to work fine. Then, following the guide, I selected "Boot from Configuration Memory Device." This process continues for a few minutes but fails at 100% with a generic error, as seen in the log here.
My apologies if this is not the right place to ask, but can anyone point me in the right direction to successfully run CVA6 on my Genesys II?
Thank you, and thank you for all your great work.