Add RISCV documentation for cv64a6_mmu

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Other

2.14k stars 651 forks source link

Closed LQUA closed 2 days ago

LQUA commented 2 days ago

Files added

new directory for all cv64a6_mmu documentation. Only the riscv part is present for the moment, the design documentation is coming soon in a next PR
generated priv-html and unpriv-html
config-define.adoc, to help using conditions in *.adoc

Files modified

machine.adoc. Asciidoc does not support operators on 'ifeval' directive. I had to define boolean variable, as it is possible to have OR and AND operators with 'ifdef' directive
added support for RVS expension in supervisor.adoc

github-actions[bot] commented 2 days ago

:heavy_check_mark: successful run, report available here.