Open AnouarZajni opened 2 months ago
👋 Hi there!
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For CV32A65X there are no debug features supported. This leaves the interrupt aspect open, see PR combo CVA6 #2502 + https://github.com/openhwgroup/core-v-verif/pull/2532 for a proposed solution.
Is there an existing CVA6 task for this?
Task Description
To align RTL and Spike-Tandem in some test scenarios (example CSR tests, interrupt tests, ...) and for functional verification purposes, upgrade Spike tandem is required to implement DPI functions to access internal spike CSR registers in read and write modes. Also, Spike should be aware about external interrupt/debug signals.
Required Changes
Required DPI functions are: 1- DPI function to write spike internal CSR registers 2- DPI function to read spike internal CSR registers 3- DPI function to update spike with interrupt asserted/de-asserted 4- DPI function to update spike with debug signals
Current Status
N/A
Risks
Some registers are not updated by spike so read return values will be wrong
Prerequisites
No response
KPI (KEY Performance Indicators)
No response
Description of Done
DPI function implemented and tested in UVM testbench
Associated PRs
No response