Unable to synthesize using Yosys

[Harshitha276]

Is there an existing CVA6 bug for this?

• [x] I have searched the existing bug issues

Bug Description

I am trying to synthesize the CVA6 core using open-source tools. Our synthesis flow involves Yosys, a synthesis tool. Because Yosys doesn't read SystemVerilog, we are using Zach's sv2v tool https://github.com/zachjs/sv2v to convert SystemVerilog to Verilog and synlig for parsing https://github.com/chipsalliance/synlig. Despite our efforts, we have encountered several issues that are preventing successful synthesis. I observed that there were tcl scripts provided for Synopsys DC. Is there a way for us to use tools like Yosys and synthesize it?

[JeanRochCoulon]

Hello, Nice to try Yosys. Unfortunately, no Yosys support is provided so far. But we are of course open for contributions !

[cliffnotes]

Jean: To create an SOC that uses CVA6, we need Synopsys or Cadence? Is that what you are saying?

[JeanRochCoulon]

No, I do not say it. Synopsys is used to do CVA6 synthesis. We have no experience with Cadence or Yosys.

[cliffnotes]

We will attempt to get Yosys working this week with the latest versions of Surelog, etc. If successful, we will try to make create layouts on ts40, gf22, ts16, and gf14. this month. If all goes well, we will be happy create CVA6 layouts for free (even for Synopsy users) if our liberty file is used. We generate our own standard cells to get around NDAs

[JeanRochCoulon]

That's a great news ! We would be please to learn more on your flow. When ready, I would be pleased to invite you to the cva6 meeting to present it.

[Moschn]

FYI, there is a project that tests compatibility of open-source system-verilog tools with popular open-source SV projects: https://chipsalliance.github.io/sv-tests/. They also include CVA6 (under the old name Ariane) in the cores category. The dashboard shows that no tool is able to compile CVA6. However, I believe the way they build CVA6 is broken as they rely on the old Makefile. I recently started to fix the build procedure on this dashboard.

In general, we mostly use verilator and synopsis tools. I believe other people have successfully used Cadence tools and Yosis before, but this usually requires some effort to read the error messages and fix the issues that pop up.

[phsauter]

We are actually able to use SV2V and our own tool SVase to successfully convert CVA6 to Verilog and then read it into Yosys. As you can see there are still a handful of patches necessary to convert some RTL features to make this toolflow handle it successfully

You can find the flow here: https://github.com/pulp-platform/cheshire-ihp130-o/tree/main/target/ihp13/pickle

And it is also described a bit here: https://arxiv.org/abs/2405.04257 And also here: https://arxiv.org/abs/2406.15107

In the future there should also be Yosys-Slang which uses the top performing Slang parser to implement a Yosys frontend, this is still in early development though.

P.S: If someone would like to work on improving this compatibility by slightly rewriting 10-20 RTL constructs I would be glad to help with the things we learned so far.

[cliffnotes]

Thank you!

My analog, SRAM, DSP teams perform well, but we have been very unsuccessful on the CPU side. Digital is not our strong suit (until recently, we went by the name "Analog Rails"). We are completely reliant on Verilator, YosysHQ and a CPU to complete our IC tools and IP to go against the EDA oligopoly. We have put over 200 man years into this and it is time to deliver.

I won't allow our company to use any of our competitors tools, so we are reliant on YosysHQ succeeding. Any help that you can offer us to see Yosys work on your project is appreciated. I will put a bunch of our new MSEEs onto rewriting 10-20 RTL constructs TODAY. Please guide us.

[phsauter]

The necessary RTL patches we apply are pretty well documented in https://github.com/pulp-platform/cheshire-ihp130-o/tree/main/target/ihp13/pickle

You would have to track down where exactly they come from and figure out how to rewrite these parts to make them go through the various tools.

But I have another question, have you ever tried the commercial YosysHQ offering Tabby CAD? It comes with SystemVerilog support, I think via Verific.

[cliffnotes]

We just started using Tabby on Monday. It helped tremendously, but we are still facing some issues. We are still working through it. We will keep you posted. Thanks for the tips. My team will follow your lead.