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openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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[BUG] Incorrect depth of Instr_queue in the specification #2350

Open AEzzejjari opened 1 month ago

AEzzejjari commented 1 month ago

Is there an existing CVA6 bug for this?

Bug Description

The instruction queue contains multiple instruction FIFOs to handle multiple parallel instructions at the same time. The number of FIFOs equals to INSTR_PER_FETCH, and the depth of each FIFO equals FIFO_DEPTH. The instruction queue also contains another FIFO for addresses in case of address prediction, with the same depth, FIFO_DEPTH. The actual depth of the instruction queue is not obvious due to this incompatibility between the address FIFO and the instruction FIFOs.

cathales commented 1 month ago

In #2375 I change how the IQ is configured.

I have started working on superscalar documentation and will fix the IQ documentation there.