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openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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cva6 Synthesis #2425

Closed Syedateeb24 closed 4 days ago

Syedateeb24 commented 1 month ago

Is there an existing CVA6 bug for this?

Bug Description

I am trying to perform synthesis of cva6 on cadence genus but i am unable to perform a successful synthesis. There are many design files in the repository which is posing a problem for me to choose the required/necessary files for synthesis. I request you to help me know the right way to approach the synthesis & help me in knowing the necessary files to perform a successful synthesis of cva6.

Syedateeb24 commented 1 month ago

Any inputs on synthesis will be highly appreciated. Thankyou

Moschn commented 1 month ago

Take a look at core/Flist.cva6. It should contain most files required for synthesis.

You can also check the Makefile for more details.

isaar-ahmad commented 1 month ago

Synthesis with Vivado is fairly straightforward. Even if your desired target is an ASIC, try synthesizing the FPGA target with Vivado first. It will provide you with the source files, that you may use as a reference for synthesis with other tools (e.g. Genus).

If you don't have Vivado, you can still generate the list of source files required for synthezising CVA6 based system on an FPGA target (e.g. Genesys 2). Note that the synthesis target for the following steps is a system (not just the core). Therefore, the list will contain memory modules, AXI crossbar and peripheral modules, apart from the CVA6 core itself :

Assume $REPO_HOME_DIR is the base of your repository . Then :

  1. Open $REPO_HOMEDIR/Makefile, look for this line and comment it out : $(MAKE) -C corev_apu/fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIODNS)

  2. Run the following in shell : cd $REPO_HOME_DIR; make fpga

  3. cd $REPO_HOME_DIR/corev_apu/fpga/scripts

  4. Look for add_sources.tcl file. This is the file that was generated when you ran Step 2. It contains all source files required for synthesis of the CVA6 system on FPGA.

You may use add_sources.tcl as a reference for your synthesis. If you are ONLY interested in the core, then look for the hierarchy i_ariane.

Hope that helps.

github-actions[bot] commented 1 week ago

👋 Hi there!

This issue seems inactive. Need more help? Feel free to update us. If there are no updates within the next few days, we'll go ahead and close this issue. 😊