search

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
Other
2.21k stars 673 forks source link

How to bring printf support in simulation environment ? #2426

Open isaar-ahmad opened 1 month ago

isaar-ahmad commented 1 month ago

Is there an existing CVA6 bug for this?

Bug Description

Hi, I found that there has been recent discussion (May 2024 - July 2024) regarding printf statement support in CVA6 simulations (see #2103 #2184 #2220 ). It seems that CVA6 simulation environment, in its current form (e.g. with Verilator), doesn't support this.

For example, Dhrystone C files [1] have debug_print statements in them. To a newcomer, this would give an initial impression that these prints should be visible somewhere in the logfiles or console output. However, a closer inspection reveals that the implementation of debug_print() function is empty. In development stage, it is common in bare-metal environments to disable print statements, so that other parts of the test can pass through.

That being said, printf statements are useful in debugging, especially when the target under debug is a CPU itself. (I only speak for myself, based on my experience with RTL verification of ARM CPUs, and some RISC-V CPUs as well).

Please advise on this :

  1. Is there any ongoing (or planned) development for C print statements ? If yes, where can we find details regarding this ?
  2. What parts of the testbench and RTL files will need major changes, if such an update is planned?

Thanks, Isaar

Code reference : [1] Dhrystone source files (dhrystone_main.c and dhrystone.c) : Fetched by install-riscv-tests.sh

JeanRochCoulon commented 1 month ago

Indeed this feature is highly requested. But as you know it is not supported. The solution would be to support pk which provides the print feature. If someone is ready to work on it, we can provide recommendations.

isaar-ahmad commented 1 month ago

Yes, please share a plan (or an outline) for the required functionality. That would be helpful in assessing whether someone (e.g. myself) can take up the task.

JeanRochCoulon commented 1 month ago

@valentinThomazic the floor is yours to explain how to proceed ;-)

valentinThomazic commented 2 weeks ago

Hey sorry for the delay, the riscv proxy kernel used to be supported in this repo (I can give some directions if needed). For it to be supported again, we would need it to be cleanly integrated to the flow. It should be possible to activate it with an env variable or a parameter for instance. The difficulty would come from the complexity of the cva6.pyscript, the verif/sim/Makefile and ./Makefile, we really don't want to add more.