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openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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[BUG] error when run smoke-tests.sh with custom instruction #2454

Closed hhhsiang closed 5 days ago

hhhsiang commented 2 months ago

Is there an existing CVA6 bug for this?

Bug Description

I want to modified the cva6 decoder to decode a custom instruction, so I use .insn pseudo instruction to present custom instruction in custom_test_template.S like this. image

However, when I run python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS by smoke-test.sh, I encountered the error：

ERROR ERROR return code: True/2, cmd:make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc elf=/home/cva6/verif/sim/out_2024-08-19/directed_asm_tests/custom_test_template.o path_var=/home/cva6/ tool_path=/home/cva6/tools/spike/bin isscomp_opts="" issrun_opts="+debug_disable=1+UVM_VERBOSITY=UVM_NONE +ntb_random_seed=1" isspostrun_opts="0x0000000080000000" log=/home/cva6/verif/sim/out_2024-08-19/veri-testharness_sim/custom_test_template.cv64a6_imafdc_sv39.log &> /home/cva6/verif/sim/out_2024-08-19/veri-testharness_sim/custom_test_template.cv64a6_imafdc_sv39.log.iss

image The error message show in custom_test_template.cv64a6_imafdc_sv39.log： image

I have set export DV_SIMULATORS=veri-testharness, I think the simulation only run with verilator.

The questions are：

  1. The .log and .vcd file are not generated after smoke-tsets.sh is finished. However, I check the code in rvfi_tracer.sv, the following code will record the executed instructions： image I think the .log file should be generated although the error happened.
  2. The rvfi_tracer.sv will determine the illegal instruction like the following： image When I run a custom instruction, It should write exception for illegal instruction in a .log file, however, no such file is actually created if error occurred.
  3. How to set my custom instruction to become a legal instruction for simulation to get VCD and .log file?

P.S. I have run riscv-tests, and all tests passed. Besides, all the vcd and .log files are generated successfully.

Gchauvon commented 1 month ago

During simulation a .dasm file is generated from the rvfi_tracer in verif/sim. It is deleted by make -C verif/sim clean_all (in smoke-tests.sh). This looks like you generated an exception during program execution most likely (ILLEGAL_INSTR).

You can have the VCD generated by setting TRACE_FAST=1.